General Documentation: EW18 Slides on using an IA simulator with Timing Estimation to provide high performance Cycle Approximate Simulation results


This paper by Lee Moore, Duncan Graham and Simon Davidmann from Imperas Software Ltd., and Felipe Rosa from Universidad Federal Rio Grande Sul Brazil presents an approach to Cycle Approximate Simulation of RISC-V Processors using Instruction Accurate simulators. It explains why timing estimation is important for the design of embedded systems and the current techniques used. Instruction Accurate simulation is introduced and then the paper explains the approach of adding timing estimation to provide fast cycle approximate simulation. Results are presented for Andes, SiFive, and Microsemi RISC-V cores. These are the slides presented.

Download document: Imperas_EW2018_RISCV_Timing_Estimation_slides.pdf