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A cooperating many-core NIOS

 
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JaVe



Joined: 11 Sep 2015
Posts: 2

PostPosted: Fri Sep 11, 2015 7:49 am    Post subject: A cooperating many-core NIOS Reply with quote

I am looking for the quickest and simplest way to implement my idea, a kind of many-core processor, which works as a super-processor with single threads.
I do have a C++ "architecture-only" simulator already, and now I want to turn it to an instruction-level simulator.
The processor has a control level (called supervisor) above the cores, which controls and organizes the job of the cores. I plan to use NIOS custom instructions for modeling the operation of the supervisor.
To do so, I need to implement the functionality of the custom instructions and to link the signals from the custom logic to the processor signals.
For example, at the beginning only one of the cores is working, the other ones are idle until the supervisor enables them; or clone the register file in one core to another.
Is it posssible in the way I intend?
Any other (better) idea?
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DuncGrah
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Joined: 27 Feb 2008
Posts: 1580
Location: United Kingdom

PostPosted: Mon Sep 14, 2015 2:52 am    Post subject: Reply with quote

Is the 'supervisor' another individual processor?

From your initial description this all appears to be straight forward.

Do you really need custom instructions in the processors?
If you decide you do, they can be added in two ways
1) using OVP you can modify the processor model source to add new instruction decodes and behavior, or
2) with Imperas you can add new instruction decodes and behavior without modifying the model by using the binary interception technology built into the Imperas professional simulator. this has the advantage that you do not modify the pre-built and tested Nios model from OVP.
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JaVe



Joined: 11 Sep 2015
Posts: 2

PostPosted: Wed Sep 16, 2015 11:20 pm    Post subject: Reply with quote

Quote:
Is the 'supervisor' another individual processor?

No, the supervisor is akin "control unit", but not for individual cores; rather to concert the work of the cores. It cooperates in some sense with the cores: the object code contains medium-sized granulates of codes equipped with pseudo-instructions (i.e. instructions which are executed by the supervisor rather than the cores, and they are skipped by the cores). The supervisor "rents" some cores and the cores are working on different code chunks independently.

Quote:
Do you really need custom instructions in the processors?

For another goal, yes. I am working on replacing some OS services with processor instructions, simply using custom instructions rather than software exceptions. For example, a binary semaphore, functionally equivalent with the traditional SW semaphore, is 30 times faster, than the traditional one, at least as implemented in Altera FPGA. To reproduce those results, I would need custom instructions for interfacing my FPGA-implemented module to the processor and also a way to implement the functionality itself.

Quote:
with Imperas you can add new instruction decodes and behavior without modifying the model by using the binary interception technology built into the Imperas professional simulator.

This sounds good, if there is way
1/ to implement my own functionality
2./ to interface it to the rest of the processor, especially if it is possible without affecting the well-tested world
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DuncGrah
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Joined: 27 Feb 2008
Posts: 1580
Location: United Kingdom

PostPosted: Thu Sep 17, 2015 12:47 am    Post subject: Reply with quote

This sounds like an interesting project.
I recommend that you contact Imperas at univ@imperas.com to discuss access to the Imperas professional product via the university program. I think this is well suited to adding custom instructions into the processor models without modification to the standard models.
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