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OVP Update to Forum Members August 2013

 
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PostPosted: Wed Aug 14, 2013 12:24 am    Post subject: OVP Update to Forum Members August 2013 Reply with quote

New OVPsim Release; New OVPsim Policy; Imperas Product Announcement

There is a new OVPsim release, 20130630, available from the OVP website. As usual, you will need to login on the Forums page to download the new release.

Please note that, as of this release, some changes have been made to the commercial version of OVPsim. OVPsim is still available for non-commercial purposes, such as for universities for research and courses. And OVPsim is still available for evaluation of OVP virtual platform technology.

For commercial use, Imperas has included the OVPSim functionality in its new Developer product range. C*DEV, S*DEV and M*DEV includes the same OVPSim virtual platform simulation capabilities as before, but also the Imperas iGen model and platform building productivity tool. C*DEV (for Controller Developer) will enable single core only simulation, S*DEV (for Standard Developer) will enable homogeneous multicore simulation, and M*DEV (for Multicore Developer) will enable full heterogeneous simulation.

Existing commercial users of OVPsim are being allowed to upgrade to S*DEV at no additional cost.

For more information, please see the following:

Imperas product announcement

*DEV product information


Imperas OVP Fast Processor Models of the ARM Cortex-A7 Family are Released
The ARM Cortex‚ÄďA7 MPCore family has become very popular for a wide variety of applications, such as mobile and networking. This processor core adds virtualization instructions to the ARMv7 architecture, as well as Long Physical Address Extensions (LPAE).

The new models have the usual OVP characteristics: - 100s of millions of instructions per second performance - Native interfaces for OVP C and SystemC/TLM-2.0 virtual platforms - Working with OVPsim, software running on these models can be debugged using GDB and Eclipse

The new models can be downloaded from www.OVPworld.org/ARM.

As is usual with OVP Fast Processor Models, example virtual platforms are available, showing various applications from simple benchmarks to booting Linux.

OVP Fast Processor Models of ARM Cores are available for ARMv4, v5, v6, and v7 architectures, and have support for additional instructions including MMU, MPU, TCM, Thumb, Thumb-2, Jazelle, SIMD, VFP, NEON, TrustZone, and Virtualization.

ARM core models available from OVP:
ARM7TDMI / 7EJ-S / 720T
ARM920T / 922T, 926EJ-S / 940T / 946E / 966E / 968E-S
ARM1136J-S / 1156T2-S / ARM1176JZ-S
Cortex-A5UP / Cortex-A5MP / Cortex-A7UP / Cortex-A7MP / Cortex-A8 / Cortex-A9UP / Cortex-A9MP
Cortex-A15UP / Cortex-A15MP
Cortex-M3 / Cortex-M4 / Cortex-M4F
Cortex-R4 / Cortex-R4F

Interesting OVP Usage Case Study: TangoTec Success with OVPsim
TangoTec, an Israeli company providing home and office networking products, has deployed OVPsim and OVP reference virtual platforms for their embedded software environment in order to enhance their software development and verification processes. The environment will be utilized on TangoTec's next-generation communications chipsets.

TangoTec was able to utilize the Imperas environment instead of having to build prototype hardware. The company was also able to leverage multiple virtual platforms running many more tests in parallel. The code morphing modeling technology including in OVP allows code execution at hundreds of millions of instructions per second, allowing for greater test throughput. These factors lead TangoTec to significantly accelerate their software development schedules, which was key for their product requirements.

Ari Todtfeld, Software Group Manager for TangoTec, noted: "The stringent test requirements around TangoTec's software applications drove the employment of a simulation-based development environment. The performance, usability and platform flexibility of the Imperas environment made it the clear choice and it has proven invaluable for the pre-silicon software development of our networking protocols, shaving months off our engineering schedule. The virtual platform based methodology also provides significant savings by avoiding custom hardware prototyping for software development."


Imperas Names Upwind Technology as Technical Support Provider in Japan
Imperas has named Upwind Technology as its technical support provider in Japan. Upwind will provide both pre- and post-sales support to the growing number of Imperas customers in Japan, spanning markets from automotive to industrial controls and consumer electronics. Tokyo NanoFarm will continue to be the sales channel for the Imperas software development and test products.

"Embedded software and systems are getting more complex, while at the same time schedules are getting shorter and test requirements larger," said Kenichi Nakamura, founder and president of Upwind Technology. "Imperas' virtual platform based products have demonstrated both technical and business success in Japan, and we are excited to help accelerate that growth. In particular, M*SDK, with its advance tools for embedded software verification, analysis and debug, including CPU-and OS-aware capabilities, brings significant value to developers in Japan."

Upwind may be contacted at jp.support@imperas.com. Tokyo NanoFarm may be contacted at yokokawa@imperas.com.


Multicore Developers Conference, May 21-22, Silicon Valley


We recently presented a paper entitled "Virtual Platform Based Software Debug and Testing for Multiprocessor/Multicore Systems" at the Multicore Developers Conference in Silicon Valley. If you are interested in a copy of the slides, please contact us at info[at]Imperas.com.

Abstract:
The design quality impact of modern electronic system complexity requires new thinking in debug and testing methodologies. Software simulation, leveraging virtual platforms, provides a powerful new approach for both functional test and analysis, including coverage, profiling, and fault injection. Moreover, this technique allows non-intrusive tool implementation, instilling test validity.

This presentation discusses the construction of very high performance (>100M instructions per second) instruction accurate virtual platforms, and presents integral, advanced debug, test and analytical capabilities with specific emphasis on OS-aware solutions. Case studies include SMP OS bring up, AMP OS debug and memory monitoring, and multiprocessor network communications testing.


Cadence CDNLive! Conference, March 12-13, Silicon Valley
We presented a paper entitled "Virtual Platform Based Software Testing for ARM-Based Systems" on Wednesday, March 13th at CDNLive in Silicon Valley. If you are interested in a copy of the slides, please contact us at info[at]Imperas.com.


New OVPsim Release Available on www.OVPworld.org
A new release of OVPsim, 20130630, was made available to users in the last week. The focus of this release is bug fixes, with many incremental changes. The powerpc32_400 processor model has been added as a new processor model for vendor power.ovpworld.org. This model supports variants m440, m460, m470 and m476.

Please check the release notes for more details.
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