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OVP Update to Forum Members February 2015

 
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PostPosted: Thu Feb 05, 2015 6:50 am    Post subject: OVP Update to Forum Members February 2015 Reply with quote

MIPS Models; MIPS EPK; MIPS and Kyma; Embedded World


MIPS Models

Models of the MIPS P-Class and M-Class Warrior CPU cores from Imagination Technologies have been released. The models of the P5600 and M51xx processor cores, as well as models of other MIPS processors, work with the Imperas and OVP simulators, including the QuantumLeap parallel simulation accelerator. The processor core models and example platforms are available from the Open Virtual Platforms website, www.OVPworld.org/MIPS. The models are also supported in the Imperas M*SDK™ advanced software development tools. In addition, the Imperas M*SDK and M*DEV™ products support the use of the Imagination Codescape Debugger for embedded software debug.

MIPS Extendable Platform Kits (EPKs)

Extendable Platform Kits™ (EPKs™) for MIPS CPU cores are now available. They are based on the functionality of Imagination’s MIPS FPGA evaluation platforms, enabling users to simulate MIPS-based systems using Imagination’s reference platforms. EPKs provide a base, a known good starting point, for users to extend the functionality of the virtual platform, to closer reflect their own platform, by adding more component models, running different operating systems or adding additional applications.

EPKs are virtual platforms (simulation models) of the target devices, including the processor model(s) for the target device plus enough peripheral models to boot an operating system or run bare metal applications. There are two generic flavors of the EPKs for MIPS, one targeting full operating systems, such as Linux, and one which focuses on Real Time Operating Systems (RTOS) such as Mentor Nucleus. OVP models of the MIPS processor cores are included in the EPKs, and for those MIPS processors which support mulitple cores, SMP Linux is supported for that EPK. For all of these initial EPKs for MIPS, many of the peripheral components of the platform are modeled, including the Ethernet component. The semi-hosting capability of the Imperas virtual platform simulator products enables connection via the Ethernet component from the EPK to the real world via the x86 host machine.

MIPS and Kyma

Recently Imperas announced that Kyma Systems has been successfully using the Imperas M*SDK™ product for virtual platform-based development of hypervisors. M*SDK enabled porting of the KVM hypervisor to support the latest MIPS cores which include hardware virtualization extensions. The OS- and CPU-aware tools included with M*SDK also enabled more comprehensive and faster testing of the hypervisor.

The KVM hypervisor is included with standard Linux distributions. Initially, Kyma ported KVM to the MIPS32® Release 2 architecture using trap and emulate technology. With the transition to the MIPS32 Release 5 architecture, including the addition of hardware virtualization extensions to the MIPS cores such as the Warrior P-class P5600 and M-class M5150 families, KVM for MIPS was re-developed to take full advantage of those virtualization instructions.

Embedded World, February 24-26, Nuremberg, Germany

Embedded World is February 24-26 in Nuremberg, Germany. Imperas is presenting a paper titled “Parallel Simulation Accelerates Embedded Software Development, Debug and Test” in Session 23, Tuesday at 14:30. While we do not have a booth at the show, our partners Imagination Technologies – MIPS again! – and Magillem will have Imperas/OVP demos in their booths. Or contact us to arrange a demo separately with us.

Here is the abstract of the paper:

For any simulation technology, the key factors for usability are performance and controllability/observability. For instruction accurate virtual platforms, the controllability and observability have been successfully addressed in various ways, including using APIs for the processor models and tools integrated in the simulation environment. In the area of performance, where near real time simulation performance is required, virtual platforms have been limited to single thread execution because of the need for determinism in the simulation. This need is driven by the loss of many of the key benefits of controllability and observability if the simulation is not repeatable. While multiple threads on multiple cores of the host x86 PC offer the hope of performance improvement, the overhead for synchronizing multiple simulation execution threads to maintain deterministic simulation results has cancelled out any performance gains realized by parallelizing the simulation.

A new synchronization algorithm has been realized, with much lower overhead, so that significant performance gains have been achieved. Performance gains of over 2x have been achieved for symmetric multiprocessor (SMP) systems simulating on a 4-core host machine, while performance gains of over 3x have been achieved for asymmetric multiprocessor (AMP) systems. The same principals have also been applied to accelerating the performance of virtual platforms where the performance bottleneck is one or more of the models used for accelerating specific applications such as image recognition.

University Work With OVP

A paper on power estimation using OVP was presented at the PATMOS 14 conference. You can find the paper here. The researchers are from UFRGS (Brazil), LIRMM (France) and PUCRS (Brazil). Here is a summary of the paper:

The growing concerns of energy efficiency and performance scalability motivate research in the area of manycore embedded systems. The software development of such systems plays an important role on the system performance, while accounting for a significant part of the total energy consumption. Thus, it becomes imperative to consider the software energy consumption at early stages of the software development. This paper proposes an instruction-driven energy analysis approach that provides an accurate and practical way of evaluating software energy cost. Results show that the accuracy of our approach varies from 0.06% to 8.05% when compared to a gate-level implementation.

The EU FP7 FlexTiles research project has developed a virtual platform of the FlexTiles Development Platform, which is built using Xilinx FPGAs. The platform includes a number of Xilinx MicroBlaze cores connected using the NoC developed by TU Eindhoven. Lead on the virtual platform is Stephan Werner of Karlsruhe Institute of Technology (KIT). You can learn more about the OVP virtual platform from this presentation , or at the FlexTiles workshop to be held on April 15th in Bochum, Germany, prior to the ARC’15 conference.

The Current OVPsim Release is 20141103.0 (November 2014)
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