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How to trigger RISC-V external interrupt handler?

 
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LattnerChen



Joined: 04 Sep 2018
Posts: 1

PostPosted: Tue Dec 04, 2018 2:56 am    Post subject: How to trigger RISC-V external interrupt handler? Reply with quote

I'm building a SystemC accelerator virtual platform, an OVP RISC-V processor model plays the role of micro-controller that programs hardware accelerators, and an OVP Platform-Level Interrupt Controller (PLIC) peripheral model connects the accelerator interrupts to the RISC-V micro-controller. I use andestech/risc-llvm-toolchain as the cross-compiler to compile the bare-metal application that is ran on the RISC-V. Currently I am searching for how to trigger external interrupt handler function in the application. However, I still don't get much useful information. Could you possibly provide any information about it or an example for reference.

Thank you.
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DuncGrah
OVP Technologist
OVP Technologist


Joined: 27 Feb 2008
Posts: 1581
Location: United Kingdom

PostPosted: Wed Jul 03, 2019 7:53 am    Post subject: Reply with quote

The PLIC can expose up to 256 external interrupts. In order to generate an interrupt to the processor you
1) need to program the PLIC correctly to enable the interrupt - this is in your software application
2) write to the interrupt input signal - this would be another device or in a testbench

You could take a look at the example Imperas\Examples\PlatformConstruction\processorExternalInterrupt
This shows an external peripheral device generating an interrupt, however, this is a different processor and not SystemC.
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