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OVP Update to Forum Members February 2013

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PostPosted: Fri Feb 08, 2013 5:05 am    Post subject: OVP Update to Forum Members February 2013 Reply with quote

Imperas Models and Tools Find Linux Bugs; ARM Cortex-A15 Models; New OVPsim Release; Europractice for EU University and Research Institute Usage

Imperas Models and Tools Find Linux Bugs

Imperas' two areas of focus – their core competencies – are high-performance processor core models and software development and test tools. These two areas of focus were highlighted last week as these models and tools were used to find two bugs in Linux:

1) The high quality and comprehensive implementation of an OVP model of an ARM processor core (Cortex-A15) enabled an Imperas customer to isolate a bug in Linaro Linux that was previously undetected using models from another model vendor. This was caused by an incorrect hypervisor mode change that could result in unpredictable behavior from the other vendors model (likely due to a bug in the virtualization instructions in the other vendors model), previously unnoticed. Unfortunately the users were not using Imperas verification, analysis and profiling (VAP) tools, and this effort to understand simulation results and find the bug took about 2 weeks.

2) The Imperas Verification, Analysis and Profiling (VAP) tools, combined with the company’s 3-D debug technology, were used to isolate a bug in a customer-specific version of Linux. This complex bug was detected within about two days of the first Linux boot on the virtual platform. The CPU- and OS-aware capabilities of the VAP tools were utilized, especially the various tracing capabilities. The tracing tools include not only instruction tracing and register change tracing, but also tracing at higher levels of abstraction, such as tracing functions, exceptions, and tracing OS tasks.

Imperas OVP Fast Processor Models of the ARM Cortex-A15 Family are Released

The ARM Cortex–A15 MP Core family has become very popular for a wide variety of applications, such as mobile and networking. This processor core adds virtualization instructions to the ARMv7 architecture, as well as Long Physical Address Extensions (LPAE). As is usual with OVP Fast Processor Models, example virtual platforms are available, showing various applications from simple benchmarks to booting Linux.

The new models have the usual OVP characteristics:
- 100s of millions of instructions per second performance
- Native interfaces for OVP C and SystemC/TLM-2.0 virtual platforms
- Working with OVPsim, software running on these models can be debugged using GDB and Eclipse.

The new models can be downloaded from http://www.ovpworld.org/processor-family-arm-cortex.

OVP Fast Processor Models of ARM Cores are available for ARMv4, v5, v6, and v7 architectures, and have support for additional instructions including MMU, MPU, TCM, Thumb, Thumb-2, Jazelle, SIMD, VFP, NEON, TrustZone, and Virtualization.

ARM cores available from OVP:
ARM7TDMI / 7EJ-S / 720T
ARM920T / 922T, 926EJ-S / 940T / 946E / 966E / 968E-S
ARM1136J-S / 1156T2-S / ARM1176JZ-S
Cortex-A5UP / Cortex-A8 / Cortex-A9UP / Cortex-A9-MP / Cortex-A15MP
Cortex-M3 / Cortex-M4
Cortex-R4 / Cortex-R4F

Cadence CDNLive! Conference, March 12-13, Silicon Valley

Imperas are presenting a paper entitled “Virtual Platform Based Software Testing for ARM-Based Systems” on Wednesday, March 13th at 2:30pm in the Hyatt Regency Hotel, Santa Clara, CA.

As electronics systems get more complex, quality becomes a much bigger issue. Solving the quality issue means improved testing methodologies, both for testing of software on individual SoCs, as well as systems involving multiple SoCs. Virtual platforms (software simulation) provide one approach, not only for basic software testing but also adding in more advanced test and analysis capabilities like code coverage, profiling, memory analysis, fault injection and more. Moreover, these tools can be implemented in a completely non-intrusive manner, adding validity to the testing methodology.

This presentation will discuss the construction of very high performance (hundreds of millions of instructions per second) instruction accurate virtual platforms using Cadence’s Virtual System Platform and Imperas’ Open Virtual Platforms (OVP) models of ARM processor cores, and will present advanced test and analytical capabilities of virtual platforms. Specific emphasis will be placed on the OS-aware testing capabilities. An example of the use of the tools and methodology for analyzing and debugging an ARM Cortex-A15 MPCore based SoC, with a hypervisor running with 2 different guest operating systems.

New OVPsim Release Available on www.OVPworld.org

A new release of OVPsim, 20121212, was made available to users in late December, 2012. The focus of this release is bug fixes, with only some incremental changes. Please check the release notes for more details.

Europractice for EU University and Research Institute Usage of OVP
Europractice Software Service (http://www.europractice.stfc.ac.uk) is distributing the OVPsim™ and M*SIM™ software development solutions from Imperas. The Europractice Software Service is an EC initiative, which provides access to state of the art development and test tools for academic institutes and government funded research laboratories. Through Europractice, professors and researchers can acquire tools for courses, as well as for research projects.

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