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OVP Virtual Platform: AlteraCycloneIII_3c120

This page provides detailed information about the OVP Virtual Platform Model of the altera.ovpworld.org AlteraCycloneIII_3c120 platform.

Licensing

Open Source Apache 2.0

Description

This platform models the Altera Cyclone III 3c120. The processor is an Altera Nios_II procesor, Nios_II_F.

Limitations

Peripherals are modeled only to the extent required to boot and run Operating Systems such as Linux.

Reference

Altera Cyclone III 3c120 Reference Guide

Location

The AlteraCycloneIII_3c120 virtual platform is located in an Imperas/OVP installation at the VLNV: altera.ovpworld.org / module / AlteraCycloneIII_3c120 / 1.0.

Platform Summary

Table : Components in platform

Platform Simulation Attributes

Table 1: Platform Simulation Attributes

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Command Line Control of the Platform

Built-in Arguments

Table 2: Platform Built-in Arguments

When running a platform in a Windows or Linux shell several command arguments can be specified. Typically there is a '-help' command which lists the commands available in the platforms.
For example: myplatform.exe -help

Some command line arguments require a value to be provided.
For example: myplatform.exe -program myimagefile.elf

Platform Specific Command Line Arguments

No platform specific command line arguments have been specified.

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Processor [altera.ovpworld.org/processor/nios_ii/1.0] instance: cpu

Processor model type: 'nios_ii' variant 'Nios_II_F' definition

Imperas OVP processor models support multiple variants and details of the variants implemented in this model can be found in:
- the Imperas installation located at ImperasLib/source/altera.ovpworld.org/processor/nios_ii/1.0/doc
- the OVP website: OVP_Model_Specific_Information_nios_ii_Nios_II_F.pdf

Description

Nios_II Family Processor Model.

Licensing

Open Source Apache 2.0

Limitations

No Custom instructions.
No Cache model.
No JTAG.

Verification

Models have been extensively tested by Imperas, and validated against tests from Altera.

Features

Barrel Shifter.
Configurable MPU.
Configurable MMU.
Shadow Register Sets.
Hardware Multiply.
Hardware Divide.
Hardware Extended Multiply.

Instance Parameters

Several parameters can be specified when a processor is instanced in a platform. For this processor instance 'cpu' it has been instanced with the following parameters:

Table 3: Processor Instance 'cpu' Parameters (Configurations)

Table 4: Processor Instance 'cpu' Parameters (Attributes)

Memory Map for processor 'cpu' bus: 'ibus'

Processor instance 'cpu' is connected to bus 'ibus' using master port 'INSTRUCTION'.

Table 5: Memory Map ( 'cpu' / 'ibus' [width: 32] )

Table 6: Bridged Memory Map ( 'cpu' / 'pb_ibus_to_smbus' / 'smbus' [width: 32] )

Memory Map for processor 'cpu' bus: 'dbus'

Processor instance 'cpu' is connected to bus 'dbus' using master port 'DATA'.

Table 7: Memory Map ( 'cpu' / 'dbus' [width: 32] )

Table 8: Bridged Memory Map ( 'cpu' / 'pb_dbus_to_smbus_1' / 'smbus' [width: 32] )

Table 9: Bridged Memory Map ( 'cpu' / 'pb_cpu_to_io' / 'iobus' [width: 32] )

Table 10: Bridged Memory Map ( 'cpu' / 'pb_dbus_to_smbus_2' / 'smbus' [width: 32] )

Net Connections to processor: 'cpu'

Table 11: Processor Net Connections ( 'cpu' )

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Peripheral Instances

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Peripheral [altera.ovpworld.org/peripheral/Uart/1.0] instance: uart_s1

Licensing

Open Source Apache 2.0

Description

Altera Avalon UART

Limitations

No Support for pin level transitions

Reference

Embedded Peripherals IP User Guide, UG-01085-11.0 11.0 June 2011

There are no configuration options set for this peripheral instance.

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Peripheral [altera.ovpworld.org/peripheral/SystemIDCore/1.0] instance: sysid

Licensing

Open Source Apache 2.0

Description

Altera Avalon System ID Core

Limitations

No Support for pin level transitions

Reference

Embedded Peripherals IP User Guide, UG-01085-11.0 11.0 June 2011

There are no configuration options set for this peripheral instance.

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Peripheral [altera.ovpworld.org/peripheral/JtagUart/1.0] instance: jtag_uart

Licensing

Open Source Apache 2.0

Description

Altera Avalon JTAG UART

Limitations

No Support for pin level transitions

Reference

Embedded Peripherals IP User Guide, UG-01085-11.0 11.0 June 2011

Table 12: Configuration options (attributes) set for instance 'jtag_uart'

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Peripheral [altera.ovpworld.org/peripheral/IntervalTimer32Core/1.0] instance: timer_1ms

Licensing

Open Source Apache 2.0

Description

Altera Avalon Interval Timer32 Core

Limitations

No Support for pin level transitions

Reference

Altera Interval Timer Core

There are no configuration options set for this peripheral instance.