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AlteraIntervalTimer64Core



OVP Peripheral Model: AlteraIntervalTimer64Core



Model Specific Information

This page provides introductory usage information for an Imperas OVP peripheral behavioral model. The page is split into sections providing specific information for this peripheral, including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.

Licensing

Open Source Apache 2.0

Description

Altera Avalon Interval Timer32 Core

Limitations

No Support for pin level transitions

Reference

Altera Interval Timer Core

Location

The IntervalTimer64Core peripheral model is located in an Imperas/OVP installation at the VLNV: altera.ovpworld.org / peripheral / IntervalTimer64Core / 1.0.



Peripheral Instance Parameters

This model accepts the following parameters:

Table : Peripheral Parameters

NameTypeDescription
timeoutPerioduns64The timout period in microSeconds (default 10000 uS)
timerFrequencyfloatThe frequency of operation in MHz (default 166MHz)
timeoutConfigenumeration
writeablePeriodbool
readableSnapshotbool
startStopControlBitsbool
timeoutPulsebool
systemResetOnTimeoutbool



Net Ports

This model has the following net ports:

Table 1: Net Ports

NameTypeMust Be ConnectedDescription
irqoutputF (False)
resetrequestoutputF (False)
timeout_pulseoutputF (False)



Bus Slave Ports

This model has the following bus slave ports:

Bus Slave Port: sp1

Table 2: Bus Slave Port: sp1

NameSize (bytes)Must Be ConnectedDescription
sp10x28F (False)

Table 3: Bus Slave Port: sp1 Registers:

NameOffsetWidth (bits)DescriptionR/Wis Volatile
reg0_status0x016
reg0_control0x416
reg0_period_00x816
reg0_period_10xc16
reg0_period_20x1016
reg0_period_30x1416
reg0_snap_00x1816
reg0_snap_10x1c16
reg0_snap_20x2016
reg0_snap_30x2416



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