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AlteraNiosIIF

Model Information


This page provides detailed information about the OVP Fast Processor Model of the Altera Nios II Nios_II_F core.
Processor IP owner is Altera Nios II. More information is available from them here.

OVP Fast Processor Model is written in C.
Provides a C API for use in C based platforms.
Provides a native C++ interface for use in SystemC TLM2 platforms.

The model is written using the OVP VMI API that provides a Virtual Machine Interface that defines the behavior of the processor.
The VMI API makes a clear line between model and simulator allowing very good optimization and world class high speed performance.

The model is provided as a binary shared object and is also available as source (different models have different licensing conditions). This allows the download and use of the model binary or the use of the source to explore and modify the model.

The model has been run through an extensive QA and regression testing process.

Parallel Simulation using Imperas QuantumLeap


Traditionally, processor models and simulators make use of one thread on the host PC. Imperas have developed a technology, called QuantumLeap, that makes use of the many host cores found in modern PC/workstations to achieve industry leading simulation performance. To find out about the Imperas parallel simulation lookup Imperas QuantumLeap. There are videos of QuantumLeap on ARM here, and MIPS here. For press information related to QuantumLeap for ARM click here or for MIPS click here.
Many of the OVP Fast Processor Models have been qualified to work with QuantumLeap - this is indicated for this model below.

Embedded Software Development tools


This model executes instructions of the target architecture and provides an interface for debug access. An interface to GDB is provided and this allows the connection of many industry standard debuggers that use the GDB/RSP interface. For more information watch the OVP video here.
The model also works with the Imperas Multicore Debugger and advanced Verification, Analysis and Profiling tools.

Instruction Set Simulator (ISS) for Altera Nios II Nios_II_F


An ISS is a software development tool that takes in instructions for a target processor and executes them. The heart of an ISS is the model of the processor. Imperas has developed a range of ISS products for use in embedded software development that utilize this fast Fast Processor Model. The Imperas Altera Nios II Nios_II_F ISS runs on Windows/Linux x86 systems and takes a cross compiled elf file of your program and allows very fast execution. The Altera Nios II Nios_II_F ISS also provides access to standard GDB/RSP debuggers and connects to the Eclipse IDE and Imperas debuggers.

Overview of Altera Nios II Nios_II_F Fast Processor Model


Model Variant name: Nios_II_F
Description:
    Nios_II Family Processor Model.
Licensing:
    Open Source Apache 2.0
Limitations:
    No Custom instructions.
    No Cache model.
    No JTAG.
    
Verification:
    Models have been extensively tested by Imperas, and validated against tests from Altera.
Features:
    Barrel Shifter.
    Configurable MPU.
    Configurable MMU.
    Shadow Register Sets.
    Hardware Multiply.
    Hardware Divide.
    Hardware Extended Multiply.

Model downloadable (needs registration and to be logged in) in package Nios_II.model for Windows32 and for Linux32
OVP simulator downloadable (needs registration and to be logged in) in package OVPsim for Windows32 and for Linux32
OVP Download page here.
OVP documentation that provides overview information on processor models is available OVP_Guide_To_Using_Processor_Models.pdf.

Full model specific documentation on the variant Nios_II_F is available OVP_Model_Specific_Information_nios_ii_Nios_II_F.pdf.

Configuration


Location: The Fast Processor Model source and object file is found in the installation VLNV tree: altera.ovpworld.org/processor/nios_ii/1.0
Processor Endian-ness: This model can be set to either endian-ness (normally by a pin, or the ELF code).
Processor ELF Code: The ELF code for this model is: 0x71
QuantumLeap Support: The processor model is qualified to run in a QuantumLeap enabled simulator.

TLM Initiator Ports (Bus Ports)

Port TypeNameWidth (bits)Description
masterINSTRUCTION32
masterDATA32

SystemC Signal Ports (Net Ports)

Port TypeNameDescription
reset_ninput
d_irq0input
d_irq1input
d_irq2input
d_irq3input
d_irq4input
d_irq5input
d_irq6input
d_irq7input
d_irq8input
d_irq9input
d_irq10input
d_irq11input
d_irq12input
d_irq13input
d_irq14input
d_irq15input
d_irq16input
d_irq17input
d_irq18input
d_irq19input
d_irq20input
d_irq21input
d_irq22input
d_irq23input
d_irq24input
d_irq25input
d_irq26input
d_irq27input
d_irq28input
d_irq29input
d_irq30input
d_irq31input

No FIFO Ports in Nios_II_F.


Exceptions

NameCodeDescription
NONE0
RESET1
HARDWARE_BREAK2
PROCESSOR_ONLY_RESET_REQUEST4
INTERNAL_INTERRUPT8
EXTERNAL_NONMASKABLE_INTERRUPT16
EXTERNAL_MASKABLE_INTERRUPT32
SUPERVISOR_ONLY_INSTRUCTION_ADDRESS64
FAST_TLB_MISS_INSTRUCTION128
DOUBLE_TLB_MISS_INSTRUCTION256
TLB_PERMISSION_VIOLATION_EXECUTE512
MPU_REGION_VIOLATION_INSTRUCTION1024
SUPERVISOR_ONLY_INSTRUCTION2048
TRAP_INSTRUCTION4096
ILLEGAL_INSTRUCTION8192
UNIMPLEMENTED_INSTRUCTION16384
BREAK_INSTRUCTION32768
SUPERVISOR_ONLY_DATA_ADDRESS65536
MISALIGNED_DATA_ADDRESS131072
MISALIGNED_DESTINATION_ADDRESS262144
DIVISION_ERROR524288
FAST_TLB_MISS_DATA1048576
DOUBLE_TLB_MISS_DATA2097152
TLB_PERMISSION_VIOLATION_READ4194304
TLB_PERMISSION_VIOLATION_WRITE8388607
MPU_REGION_VIOLATION_DATA8388607

Execution Modes

ModeCodeDescription
VM_MODE_KERNEL0
VM_MODE_USER1
VM_MODE_KERNEL_MPU2
VM_MODE_USER_MPU3

More Detailed Information

The Nios_II_F OVP Fast Processor Model also has parameters, model commands, and many registers.
The model may also have hierarchy or be multicore and have other attributes and capabilities.
To see this information, please have a look at the model variant specific documents.
Click here to see the detailed document OVP_Model_Specific_Information_nios_ii_Nios_II_F.pdf.

Other Sites/Pages with similar information

Information on the Nios_II_F OVP Fast Processor Model can also be found on other web sites:
www.imperas.com has more information on the model library.



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