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AlteraPerformanceCounterCore



OVP Peripheral Model: AlteraPerformanceCounterCore



Model Specific Information

This page provides introductory usage information for an Imperas OVP peripheral behavioral model. The page is split into sections providing specific information for this peripheral, including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.

Licensing

Open Source Apache 2.0

Description

Altera Avalon Performance Counter Core

Limitations

No Support for pin level transitions

Reference

Embedded Peripherals IP User Guide, UG-01085-11.0 11.0 June 2011

Location

The PerformanceCounterCore peripheral model is located in an Imperas/OVP installation at the VLNV: altera.ovpworld.org / peripheral / PerformanceCounterCore / 1.0.



Peripheral Instance Parameters

This model accepts the following parameters:

Table : Peripheral Parameters

NameTypeDescription
Countersuns64



Bus Slave Ports

This model has the following bus slave ports:

Bus Slave Port: sp1

Table 1: Bus Slave Port: sp1

NameSize (bytes)Must Be ConnectedDescription
sp10x80F (False)

Table 2: Bus Slave Port: sp1 Registers:

NameOffsetWidth (bits)DescriptionR/Wis Volatile
reg0_t0lo0x032
reg0_t0hi0x432
reg0_t0ev0x832
reg0_t1lo0xc32
reg0_t1hi0x1032
reg0_t1ev0x1432
reg0_t2lo0x1832
reg0_t2hi0x1c32
reg0_t2ev0x2032
reg0_t3lo0x2432
reg0_t3hi0x2832
reg0_t3ev0x2c32
reg0_t4lo0x3032
reg0_t4hi0x3432
reg0_t4ev0x3832
reg0_t5lo0x3c32
reg0_t5hi0x4032
reg0_t5ev0x4432



AlteraPeripherals
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