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AlteraRSTMGR



OVP Peripheral Model: AlteraRSTMGR



Model Specific Information

This page provides introductory usage information for an Imperas OVP peripheral behavioral model. The page is split into sections providing specific information for this peripheral, including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.

Description

Altera Cyclone V Reset Manager

Limitations

Only register mpumodrst cpu0 and cpu1 reset functionality is implemented

Licensing

Open Source Apache 2.0

Reference

Cyclone V Device Handbook Volume 3: Hard Processor System Technical Reference Manual cv_5v4 2013.12.30

Location

The RSTMGR peripheral model is located in an Imperas/OVP installation at the VLNV: altera.ovpworld.org / peripheral / RSTMGR / 1.0.



Net Ports

This model has the following net ports:

Table : Net Ports

NameTypeMust Be ConnectedDescription
cpu0ResetoutputF (False)
cpu1ResetoutputF (False)



Bus Slave Ports

This model has the following bus slave ports:

Bus Slave Port: bport1

Table 1: Bus Slave Port: bport1

NameSize (bytes)Must Be ConnectedDescription
bport10x1000T (True)

Table 2: Bus Slave Port: bport1 Registers:

NameOffsetWidth (bits)DescriptionR/Wis Volatile
REGS_stat0x032
REGS_ctrl0x432
REGS_counts0x832
REGS_mpumodrst0x1032
REGS_permodrst0x1432
REGS_per2modrst0x1832
REGS_brgmodrst0x1c32
REGS_miscmodrst0x2032



Platforms that use this peripheral component

Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.

Table 3: Publicly available platforms using peripheral 'RSTMGR'

Platform NameVendor
AlteraCycloneV_HPSaltera.ovpworld.org
AlteraCycloneV_HPSaltera.ovpworld.org



AlteraPeripherals
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