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AlteraSystemIDCore



OVP Peripheral Model: AlteraSystemIDCore



Model Specific Information

This page provides introductory usage information for an Imperas OVP peripheral behavioral model. The page is split into sections providing specific information for this peripheral, including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.

Licensing

Open Source Apache 2.0

Description

Altera Avalon System ID Core

Limitations

No Support for pin level transitions

Reference

Embedded Peripherals IP User Guide, UG-01085-11.0 11.0 June 2011

Location

The SystemIDCore peripheral model is located in an Imperas/OVP installation at the VLNV: altera.ovpworld.org / peripheral / SystemIDCore / 1.0.



Peripheral Instance Parameters

This model accepts the following parameters:

Table : Peripheral Parameters

NameTypeDescription
iduns64
timestampuns64



Bus Slave Ports

This model has the following bus slave ports:

Bus Slave Port: sp1

Table 1: Bus Slave Port: sp1

NameSize (bytes)Must Be ConnectedDescription
sp10x8F (False)

Table 2: Bus Slave Port: sp1 Registers:

NameOffsetWidth (bits)DescriptionR/Wis Volatile
reg0_id0x032
reg0_timestamp0x432



Platforms that use this peripheral component

Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.

Table 3: Publicly available platforms using peripheral 'SystemIDCore'

Platform NameVendor
AlteraCycloneIII_3c120altera.ovpworld.org
AlteraCycloneIII_3c120altera.ovpworld.org



AlteraPeripherals
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