LIBRARY  |  COMPANIES |   PLATFORMS |   PROCESSORS |   PERIPHERALS
AlteraUart



OVP Peripheral Model: AlteraUart



Model Specific Information

This page provides introductory usage information for an Imperas OVP peripheral behavioral model. The page is split into sections providing specific information for this peripheral, including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.

Licensing

Open Source Apache 2.0

Description

Altera Avalon UART

Limitations

No Support for pin level transitions

Reference

Embedded Peripherals IP User Guide, UG-01085-11.0 11.0 June 2011

Location

The Uart peripheral model is located in an Imperas/OVP installation at the VLNV: altera.ovpworld.org / peripheral / Uart / 1.0.



Peripheral Instance Parameters

This model accepts the following parameters:

Table : Peripheral Parameters

NameTypeDescription
bauduns64
dataBitsuns64
fixedBauduns64
parityenumeration
stopBitsuns64
syncRegDepthuns64
useCtsRtsuns64
useEopRegisteruns64
consoleboolIf specified, port number is ignored, and a console pops up automatically
portnumuns32If set, listen on this port. If set to zero, allocate a port from the pool and listen on that.
infilestringName of file to use for device source
outfilestringName of file to write device output
portFilestringIf portnum was specified as zero, write the port number to this file when it's known
logboolIf specified, serial output will go to simulator log
finishOnDisconnectboolIf set, disconnecting the port will cause the simulation to finish
connectnonblockingboolIf set, simulation can begin before the connection is made
xcharsuns32Width of console in characters
ycharsuns32Height of console in characters
recordstringRecord external events into this file
replaystringReplay external events from this file



Net Ports

This model has the following net ports:

Table 1: Net Ports

NameTypeMust Be ConnectedDescription
irqoutputF (False)
endofpacketoutputF (False)
dataavailableoutputF (False)
readyfordataoutputF (False)
RXDinputF (False)
CTSinputF (False)
TXDoutputF (False)
RTSoutputF (False)



Bus Slave Ports

This model has the following bus slave ports:

Bus Slave Port: sp1

Table 2: Bus Slave Port: sp1

NameSize (bytes)Must Be ConnectedDescription
sp10x20F (False)

Table 3: Bus Slave Port: sp1 Registers:

NameOffsetWidth (bits)DescriptionR/Wis Volatile
reg0_rxdata0x032
reg0_txdata0x432
reg0_status0x832
reg0_control0xc32
reg0_divisor0x1032
reg0_eop0x1432



Platforms that use this peripheral component

Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.

Table 4: Publicly available platforms using peripheral 'Uart'

Platform NameVendor
AlteraCycloneIII_3c120altera.ovpworld.org
AlteraCycloneIII_3c120altera.ovpworld.org



AlteraPeripherals
Page was generated in 0.0170 seconds