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ArmCortexA15MPx2

Model Information


This page provides detailed information about the OVP Fast Processor Model of the ARM Cortex-A15MPx2 core.
Processor IP owner is ARM Holdings. More information is available from them here.

OVP Fast Processor Model is written in C.
Provides a C API for use in C based platforms.
Provides a native C++ interface for use in SystemC TLM2 platforms.

The model is written using the OVP VMI API that provides a Virtual Machine Interface that defines the behavior of the processor.
The VMI API makes a clear line between model and simulator allowing very good optimization and world class high speed performance.

The model is provided as a binary shared object and is also available as source (different models have different licensing conditions). This allows the download and use of the model binary or the use of the source to explore and modify the model.

The model has been run through an extensive QA and regression testing process.

Parallel Simulation using Imperas QuantumLeap


Traditionally, processor models and simulators make use of one thread on the host PC. Imperas have developed a technology, called QuantumLeap, that makes use of the many host cores found in modern PC/workstations to achieve industry leading simulation performance. To find out about the Imperas parallel simulation lookup Imperas QuantumLeap. There are videos of QuantumLeap on ARM here, and MIPS here. For press information related to QuantumLeap for ARM click here or for MIPS click here.
Many of the OVP Fast Processor Models have been qualified to work with QuantumLeap - this is indicated for this model below.

Embedded Software Development tools


This model executes instructions of the target architecture and provides an interface for debug access. An interface to GDB is provided and this allows the connection of many industry standard debuggers that use the GDB/RSP interface. For more information watch the OVP video here.
The model also works with the Imperas Multicore Debugger and advanced Verification, Analysis and Profiling tools.

Instruction Set Simulator (ISS) for ARM Cortex-A15MPx2


An ISS is a software development tool that takes in instructions for a target processor and executes them. The heart of an ISS is the model of the processor. Imperas has developed a range of ISS products for use in embedded software development that utilize this fast Fast Processor Model. The Imperas ARM Cortex-A15MPx2 ISS runs on Windows/Linux x86 systems and takes a cross compiled elf file of your program and allows very fast execution. The ARM Cortex-A15MPx2 ISS also provides access to standard GDB/RSP debuggers and connects to the Eclipse IDE and Imperas debuggers.

Overview of ARM Cortex-A15MPx2 Fast Processor Model


Model Variant name: Cortex-A15MPx2
Description:
    ARM Processor Model
Licensing:
    Usage of binary model under license governing simulator usage.
    
    Note that for models of ARM CPUs the license includes the following terms:
    
    Licensee is granted a non-exclusive, worldwide, non-transferable, revocable licence to:
    
    If no source is being provided to the Licensee: use and copy only (no modifications rights are granted) the model for the sole purpose of designing, developing, analyzing, debugging, testing, verifying, validating and optimizing software which: (a) (i) is for ARM based systems; and (ii) does not incorporate the ARM Models or any part thereof; and (b) such ARM Models may not be used to emulate an ARM based system to run application software in a production or live environment.
    
    If source code is being provided to the Licensee: use, copy and modify the model for the sole purpose of designing, developing, analyzing, debugging, testing, verifying, validating and optimizing software which: (a) (i) is for ARM based systems; and (ii) does not incorporate the ARM Models or any part thereof; and (b) such ARM Models may not be used to emulate an ARM based system to run application software in a production or live environment.
    
    In the case of any Licensee who is either or both an academic or educational institution the purposes shall be limited to internal use.
    
    Except to the extent that such activity is permitted by applicable law, Licensee shall not reverse engineer, decompile, or disassemble this model. If this model was provided to Licensee in Europe, Licensee shall not reverse engineer, decompile or disassemble the Model for the purposes of error correction.
    
    The License agreement does not entitle Licensee to manufacture in silicon any product based on this model.
    
    The License agreement does not entitle Licensee to use this model for evaluating the validity of any ARM patent.
    
    Source of model available under separate Imperas Software License Agreement.
Limitations:
    Instruction pipelines are not modeled in any way. All instructions are assumed to complete immediately. This means that instruction barrier instructions (e.g. ISB, CP15ISB) are treated as NOPs, with the exception of any undefined instruction behavior, which is modeled. The model does not implement speculative fetch behavior. The branch cache is not modeled.
    Caches and write buffers are not modeled in any way. All loads, fetches and stores complete immediately and in order, and are fully synchronous (as if the memory was of Strongly Ordered or Device-nGnRnE type). Data barrier instructions (e.g. DSB, CP15DSB) are treated as NOPs, with the exception of any undefined instruction behavior, which is modeled. Cache manipulation instructions are implemented as NOPs, with the exception of any undefined instruction behavior, which is modeled.
    Real-world timing effects are not modeled: all instructions are assumed to complete in a single cycle.
    Performance Monitors are implemented as a register interface only.
    TLBs are architecturally-accurate but not device accurate. This means that all TLB maintenance and address translation operations are fully implemented but the cache is larger than in the real device.
Verification:
    Models have been extensively tested by Imperas. ARM Cortex-A models have been successfully used by customers to simulate SMP Linux, Ubuntu Desktop, VxWorks and ThreadX on Xilinx Zynq virtual platforms.
Features:
    Large physical address extension is implemented.
    Thumb-2 instructions are supported.
    Trivial Jazelle extension is implemented.
    SIMD instructions are implemented.
    NEON is implemented.
    VFP is implemented.
    Security extensions are implemented (also known as TrustZone). Non-secure accesses can be made visible externally by connecting the processor to a 41-bit physical bus, in which case bits 39..0 give the true physical address and bit 40 is the NS bit.
    Virtualization extensions are implemented.
    VMSA stage 1 secure, non-secure and Hypervisor address translation is implemented. VMSA stage 2 address translation is implemented.
    Generic Timer is present. Use parameter override_timerScaleFactor to specify the counter rate as a fraction of the processor MIPS rate (e.g. 10 implies Generic Timer counters increment once every 10 processor instructions).
    GIC block is implemented (GICv2, including security extensions). Accesses to GIC registers can be viewed externally by connecting to the 32-bit GICRegisters bus port. Secure register accesses are at offset 0x0 on this bus; for example, a secure access to GIC register GICD_CTLR can be observed by monitoring address 0x00001000. Non-secure accesses are at offset 0x80000000 on this bus; for example, a non-secure access to GIC register GICD_CTLR can be observed by monitoring address 0x80001000

Model downloadable (needs registration and to be logged in) in package arm.model for Windows32 and for Linux32
OVP simulator downloadable (needs registration and to be logged in) in package OVPsim for Windows32 and for Linux32
OVP Download page here.
OVP documentation that provides overview information on processor models is available OVP_Guide_To_Using_Processor_Models.pdf.

Full model specific documentation on the variant Cortex-A15MPx2 is available OVP_Model_Specific_Information_arm_Cortex-A15MPx2.pdf.

Configuration


Location: The Fast Processor Model source and object file is found in the installation VLNV tree: arm.ovpworld.org/processor/arm/1.0
Processor Endian-ness: This model can be set to either endian-ness (normally by a pin, or the ELF code).
Processor ELF Code: The ELF code for this model is: 0x28
QuantumLeap Support: The processor model is qualified to run in a QuantumLeap enabled simulator.

TLM Initiator Ports (Bus Ports)

Port TypeNameWidth (bits)Description
masterINSTRUCTION32
masterDATA32
masterGICRegisters32

SystemC Signal Ports (Net Ports)

Port TypeNameDescription
SPI32input
SPI33input
SPI34input
SPI35input
SPI36input
SPI37input
SPI38input
SPI39input
SPI40input
SPI41input
SPI42input
SPI43input
SPI44input
SPI45input
SPI46input
SPI47input
SPI48input
SPI49input
SPI50input
SPI51input
SPI52input
SPI53input
SPI54input
SPI55input
SPI56input
SPI57input
SPI58input
SPI59input
SPI60input
SPI61input
SPI62input
SPI63input
SPI64input
SPI65input
SPI66input
SPI67input
SPI68input
SPI69input
SPI70input
SPI71input
SPI72input
SPI73input
SPI74input
SPI75input
SPI76input
SPI77input
SPI78input
SPI79input
SPI80input
SPI81input
SPI82input
SPI83input
SPI84input
SPI85input
SPI86input
SPI87input
SPI88input
SPI89input
SPI90input
SPI91input
SPI92input
SPI93input
SPI94input
SPI95input
SPIVectorinput
periphResetinput
CNTVIRQ_CPU0output
CNTPSIRQ_CPU0output
CNTPNSIRQ_CPU0output
CNTPHPIRQ_CPU0output
IRQOUT_CPU0output
FIQOUT_CPU0output
VINITHI_CPU0input
CFGEND_CPU0input
CFGTE_CPU0input
reset_CPU0input
fiq_CPU0input
irq_CPU0input
vfiq_CPU0input
virq_CPU0input
AXI_SLVERR_CPU0input
CP15SDISABLE_CPU0input
CNTVIRQ_CPU1output
CNTPSIRQ_CPU1output
CNTPNSIRQ_CPU1output
CNTPHPIRQ_CPU1output
IRQOUT_CPU1output
FIQOUT_CPU1output
VINITHI_CPU1input
CFGEND_CPU1input
CFGTE_CPU1input
reset_CPU1input
fiq_CPU1input
irq_CPU1input
vfiq_CPU1input
virq_CPU1input
AXI_SLVERR_CPU1input
CP15SDISABLE_CPU1input

No FIFO Ports in Cortex-A15MPx2.


Exceptions

NameCodeDescription
Reset0
Undefined1
SupervisorCall2
SecureMonitorCall3
HypervisorCall4
PrefetchAbort5
DataAbort6
HypervisorTrap7
IRQ8
FIQ9

Execution Modes

ModeCodeDescription
User16
FIQ17
IRQ18
Supervisor19
Monitor22
Abort23
Hypervisor26
Undefined27
System31

More Detailed Information

The Cortex-A15MPx2 OVP Fast Processor Model also has parameters, model commands, and many registers.
The model may also have hierarchy or be multicore and have other attributes and capabilities.
To see this information, please have a look at the model variant specific documents.
Click here to see the detailed document OVP_Model_Specific_Information_arm_Cortex-A15MPx2.pdf.

Other Sites/Pages with similar information

Information on the Cortex-A15MPx2 OVP Fast Processor Model can also be found on other web sites:
www.cpu-models.org has a page on the ARM Cortex-A15MPx2
www.fast-model-tools-user-guide.com has a page on the ARM Cortex-A15MPx2
www.fast-processor-models.org has a page on the ARM Cortex-A15MPx2
www.processor-models.org has a page on the ARM Cortex-A15MPx2
www.cpu-model-simulink.org has a page on the ARM Cortex-A15MPx2
www.imperas.com has more information on the model library



ArmHoldingsProcessors
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