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ArmCortexM3

Model Information


This page provides detailed information about the OVP Fast Processor Model of the ARM Cortex-M3 core.
Processor IP owner is ARM Holdings. More information is available from them here.

OVP Fast Processor Model is written in C.
Provides a C API for use in C based platforms.
Provides a native C++ interface for use in SystemC TLM2 platforms.

The model is written using the OVP VMI API that provides a Virtual Machine Interface that defines the behavior of the processor.
The VMI API makes a clear line between model and simulator allowing very good optimization and world class high speed performance.

The model is provided as a binary shared object and is also available as source (different models have different licensing conditions). This allows the download and use of the model binary or the use of the source to explore and modify the model.

The model has been run through an extensive QA and regression testing process.

Parallel Simulation using Imperas QuantumLeap


Traditionally, processor models and simulators make use of one thread on the host PC. Imperas have developed a technology, called QuantumLeap, that makes use of the many host cores found in modern PC/workstations to achieve industry leading simulation performance. To find out about the Imperas parallel simulation lookup Imperas QuantumLeap. There are videos of QuantumLeap on ARM here, and MIPS here. For press information related to QuantumLeap for ARM click here or for MIPS click here.
Many of the OVP Fast Processor Models have been qualified to work with QuantumLeap - this is indicated for this model below.

Embedded Software Development tools


This model executes instructions of the target architecture and provides an interface for debug access. An interface to GDB is provided and this allows the connection of many industry standard debuggers that use the GDB/RSP interface. For more information watch the OVP video here.
The model also works with the Imperas Multicore Debugger and advanced Verification, Analysis and Profiling tools.

Instruction Set Simulator (ISS) for ARM Cortex-M3


An ISS is a software development tool that takes in instructions for a target processor and executes them. The heart of an ISS is the model of the processor. Imperas has developed a range of ISS products for use in embedded software development that utilize this fast Fast Processor Model. The Imperas ARM Cortex-M3 ISS runs on Windows/Linux x86 systems and takes a cross compiled elf file of your program and allows very fast execution. The ARM Cortex-M3 ISS also provides access to standard GDB/RSP debuggers and connects to the Eclipse IDE and Imperas debuggers.

Overview of ARM Cortex-M3 Fast Processor Model


Model Variant name: Cortex-M3
Description:
    ARMM Processor Model
Licensing:
    Usage of binary model under license governing simulator usage.
    
    Note that for models of ARM CPUs the license includes the following terms:
    
    Licensee is granted a non-exclusive, worldwide, non-transferable, revocable licence to:
    
    If no source is being provided to the Licensee: use and copy only (no modifications rights are granted) the model for the sole purpose of designing, developing, analyzing, debugging, testing, verifying, validating and optimizing software which: (a) (i) is for ARM based systems; and (ii) does not incorporate the ARM Models or any part thereof; and (b) such ARM Models may not be used to emulate an ARM based system to run application software in a production or live environment.
    
    If source code is being provided to the Licensee: use, copy and modify the model for the sole purpose of designing, developing, analyzing, debugging, testing, verifying, validating and optimizing software which: (a) (i) is for ARM based systems; and (ii) does not incorporate the ARM Models or any part thereof; and (b) such ARM Models may not be used to emulate an ARM based system to run application software in a production or live environment.
    
    In the case of any Licensee who is either or both an academic or educational institution the purposes shall be limited to internal use.
    
    Except to the extent that such activity is permitted by applicable law, Licensee shall not reverse engineer, decompile, or disassemble this model. If this model was provided to Licensee in Europe, Licensee shall not reverse engineer, decompile or disassemble the Model for the purposes of error correction.
    
    The License agreement does not entitle Licensee to manufacture in silicon any product based on this model.
    
    The License agreement does not entitle Licensee to use this model for evaluating the validity of any ARM patent.
    
    The License agreement does not entitle Licensee to use the model to emulate an ARM based system to run application software in a production or live environment.
    
    Source of model available under separate Imperas Software License Agreement.
Limitations:
    Performance Monitors are not implemented.
    Debug Extension and related blocks are not implemented.
Verification:
    Models have been extensively tested by Imperas. ARM Cortex-M models have been successfully used by customers to simulate the Micrium uC/OS-II kernel and FreeRTOS.
Features:
    The model is configured with 16 interrupts and 3 priority bits (use override_numInterrupts and override_priorityBits parameters to change these).
    Thumb-2 instructions are supported.
    MPU is present. Use parameter override_MPU_TYPE to disable it or change the number of MPU regions if required.
    SysTick timer is present. Use parameter SysTickPresent to disable it if required.
    FPU extension is not present. Use parameter override_MVFR0 to enable it if required.
    DSP extension is not present. Use parameter override_InstructionAttributes3 to enable it if required.
    Bit-band region is present. Use parameter BitBandPresent to disable it if required.
Unpredictable Behavior:
    Many instruction behaviors are described in the ARM ARM as CONSTRAINED UNPREDICTABLE. This section describes how such situations are handled by this model.
Equal Target Registers:
    Some instructions allow the specification of two target registers (for example, double-width SMULL, or some VMOV variants), and such instructions are CONSTRAINED UNPREDICTABLE if the same target register is specified in both positions. In this model, such instructions are treated as UNDEFINED.
Floating Point Load/Store Multiple Lists:
    Instructions that load or store a list of floating point registers (e.g. VSTM, VLDM, VPUSH, VPOP) are CONSTRAINED UNPREDICTABLE if either the uppermost register in the specified range is greater than 32 or (for 64-bit registers) if more than 16 registers are specified. In this model, such instructions are treated as UNDEFINED.
If-Then (IT) Block Constraints:
    Where the behavior of an instruction in an if-then (IT) block is described as CONSTRAINED UNPREDICTABLE, this model treats that instruction as UNDEFINED.
Use of R13:
    Use of R13 is described as CONSTRAINED UNPREDICTABLE in many circumstances. This model allows R13 to be used like any other GPR.
Use of R15:
    Use of R15 is described as CONSTRAINED UNPREDICTABLE in many circumstances. This model allows such use to be configured using the parameter "unpredictableR15" as follows:
    Value "undefined": any reference to R15 in such a situation is treated as UNDEFINED;
    Value "nop": any reference to R15 in such a situation causes the instruction to be treated as a NOP;
    Value "raz_wi": any reference to R15 in such a situation causes the instruction to be treated as a RAZ/WI (that is, R15 is read as zero and write-ignored);
    Value "execute": any reference to R15 in such a situation is executed using the current value of R15 on read, and writes to R15 are allowed.
    Value "assert": any reference to R15 in such a situation causes the simulation to halt with an assertion message (allowing any such unpredictable uses to be easily identified).
    In this variant, the default value of "unpredictableR15" is "execute".

Model downloadable (needs registration and to be logged in) in package armm.model for Windows32 and for Linux32
OVP simulator downloadable (needs registration and to be logged in) in package OVPsim for Windows32 and for Linux32
OVP Download page here.
OVP documentation that provides overview information on processor models is available OVP_Guide_To_Using_Processor_Models.pdf.

Full model specific documentation on the variant Cortex-M3 is available OVP_Model_Specific_Information_armm_Cortex-M3.pdf.

Configuration


Location: The Fast Processor Model source and object file is found in the installation VLNV tree: arm.ovpworld.org/processor/armm/1.0
Processor Endian-ness: This model can be set to either endian-ness (normally by a pin, or the ELF code).
Processor ELF Code: The ELF code for this model is: 0x28
QuantumLeap Support: The processor model is qualified to run in a QuantumLeap enabled simulator.

TLM Initiator Ports (Bus Ports)

Port TypeNameWidth (bits)Description
masterINSTRUCTION32
masterDATA32

SystemC Signal Ports (Net Ports)

Port TypeNameDescription
sysResetReqoutput
intISSoutput
eventOutoutput
lockupoutput
intinput
resetinput
nmiinput
eventIninput
int0input
int1input
int2input
int3input
int4input
int5input
int6input
int7input
int8input
int9input
int10input
int11input
int12input
int13input
int14input
int15input

No FIFO Ports in Cortex-M3.


Exceptions

NameCodeDescription
None0
Reset1
NMI2
HardFault3
MemManage4
BusFault5
UsageFault6
SVCall11
DebugMonitor12
PendSV14
SysTick15
ExternalInt00016
ExternalInt00117
ExternalInt00218
ExternalInt00319
ExternalInt00420
ExternalInt00521
ExternalInt00622
ExternalInt00723
ExternalInt00824
ExternalInt00925
ExternalInt00a26
ExternalInt00b27
ExternalInt00c28
ExternalInt00d29
ExternalInt00e30
ExternalInt00f31

Execution Modes

ModeCodeDescription
Thread0
Handler1

More Detailed Information

The Cortex-M3 OVP Fast Processor Model also has parameters, model commands, and many registers.
The model may also have hierarchy or be multicore and have other attributes and capabilities.
To see this information, please have a look at the model variant specific documents.
Click here to see the detailed document OVP_Model_Specific_Information_armm_Cortex-M3.pdf.

Other Sites/Pages with similar information

Information on the Cortex-M3 OVP Fast Processor Model can also be found on other web sites:
www.imperas.com has more information on the model library.



ArmHoldingsProcessors
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