OVP Virtual Platform: ArmCortexMFreeRTOS
What is a Bare Metal Platform?
A 'Bare Metal' Platform consists of a single processor with memory available over its complete address range.
This is ideal for execution of a user application that has been compiled for the target processor core using cross-compilation.
Obtaining the ArmCortexMFreeRTOS platform and the OVP Simulator
The source and binary of the bare metal platforms are part of the OVP/Imperas downloads and live on a VLNV (Vendor Library Name Version) path.
To download from OVPworld, browse the OVP downloads page and download the OVPsim package. Click here to browse available downloads.
When installed this platform is found in your installation here: ImperasLib/source/imperas.ovpworld.org/platform/ArmCortexMFreeRTOS/1.0
Running the Bare Metal Platform
1. Run the installer to install into a local directory on your PC. We recommend you use a path without spaces, for example your home directory
2. Enter the Demo Directory IMPERAS_HOME/Demo/ArmCortexMFreeRTOS
3. On Windows, double-click on the batch file xx.bat and on Linux run the script xx.sh to run a simple application elf file on the Bare Metal Platform.
You will see output something like:
Info (ARM_NEWLIB_RDI_HEAP_INFO) RDI heap_base=0xc0000000
Info (ARM_NEWLIB_RDI_EXIT) Process has ended (exit)
Info CPU 'CPU1' STATISTICS
Info Type : arm
Info Nominal MIPS : 100
Info Final program counter : 0x91a4
Info Simulated instructions: 4,175
Info SIMULATION TIME STATISTICS
Info Simulated time : 0.00 seconds
Info User time : 0.02 seconds
Info System time : 0.00 seconds
Setting Up for Re-building the Application
To rebuild the application and create the elf file you will need 3 things:
- Cross-Compiler toolchain for thi processor
- An OVP Installation
- MSYS / MINGW environment (Windows Users Only)
Download and Installing the Cross-Compiler Toolchain
To download an appropriate tool chain, browse the OVP downloads page and download the package. Click here to browse.
If there is not one available please ask on the forum.
Once downloaded run the installer <packageName>.Windows32.exe for Windows and <packageName>.Linux32.exe for Linux
to install on your PC.
Installing MSYS / MINGW Environment (Windows Users Only)
Obtaining and installing the MSYS and MINGW environment is described in Imperas_Installation_and_Getting_Started.pdf.
You will need to be in the Demo/'baremetaldemodir' directory using an MSYS shell for Windows or a Linux shell.Re-building the Application
> make applicationRe-building the Bare Metal Platform
> make platformExecuting the application on the platform
You can just double click on the .bat file as done previously, or you can run from the msys command line:
> ./BareMetal.OS.exe hello.CROSS.elf
This page provides detailed information about the OVP Virtual Platform Model of the imperas.ovpworld.org ArmCortexMFreeRTOS
Platform for FreeRTOS bring
Open Source Apache 2.0
BareMetal platform for bring up of FreeRTOS on ARM Cortex-M3 processor
The ArmCortexMFreeRTOS virtual platform is located in an Imperas/OVP installation at the VLNV: imperas.ovpworld.org / platform / ArmCortexMFreeRTOS / 1.0.
Table : Components in platform
Platform Simulation Attributes
Table 1: Platform Simulation Attributes
|stoponctrlc||stoponctrlc||Stop on control-C|
Command Line Control of the Platform
Table 2: Platform Built-in Arguments
|allargs||allargs||The Command line parser will accept the complete imperas argument set. Note that this option is ignored in some Imperas products|
When running a platform in a Windows or Linux shell several command arguments can be specified. Typically there is a '-help' command which lists the commands available in the platforms.
For example: myplatform.exe -help
Some command line arguments require a value to be provided.
For example: myplatform.exe -program myimagefile.elf
Platform Specific Command Line Arguments
Table 3: Platform Arguments
|rtos||stringvar||the FreeRTOS image|
Processor [arm.ovpworld.org/processor/armm/1.0] instance: cpu1
Processor model type: 'armm' variant 'Cortex-M3' definition
Imperas OVP processor models support multiple variants and details of the variants implemented in this model can be found in:
- the Imperas installation located at ImperasLib/source/arm.ovpworld.org/processor/armm/1.0/doc
- the OVP website: OVP_Model_Specific_Information_armm_Cortex-M3.pdf
ARMM Processor Model
Usage of binary model under license governing simulator usage.
Note that for models of ARM CPUs the license includes the following terms:
Licensee is granted a non-exclusive, worldwide, non-transferable, revocable licence to:
If no source is being provided to the Licensee: use and copy only (no modifications rights are granted) the model for the sole purpose of designing, developing, analyzing, debugging, testing, verifying, validating and optimizing software which: (a) (i) is for ARM based systems; and (ii) does not incorporate the ARM Models or any part thereof; and (b) such ARM Models may not be used to emulate an ARM based system to run application software in a production or live environment.
If source code is being provided to the Licensee: use, copy and modify the model for the sole purpose of designing, developing, analyzing, debugging, testing, verifying, validating and optimizing software which: (a) (i) is for ARM based systems; and (ii) does not incorporate the ARM Models or any part thereof; and (b) such ARM Models may not be used to emulate an ARM based system to run application software in a production or live environment.
In the case of any Licensee who is either or both an academic or educational institution the purposes shall be limited to internal use.
Except to the extent that such activity is permitted by applicable law, Licensee shall not reverse engineer, decompile, or disassemble this model. If this model was provided to Licensee in Europe, Licensee shall not reverse engineer, decompile or disassemble the Model for the purposes of error correction.
The License agreement does not entitle Licensee to manufacture in silicon any product based on this model.
The License agreement does not entitle Licensee to use this model for evaluating the validity of any ARM patent.
The License agreement does not entitle Licensee to use the model to emulate an ARM based system to run application software in a production or live environment.
Source of model available under separate Imperas Software License Agreement.
Performance Monitors are not implemented.
Debug Extension and related blocks are not implemented.
Models have been extensively tested by Imperas. ARM Cortex-M models have been successfully used by customers to simulate the Micrium uC/OS-II kernel and FreeRTOS.
The model is configured with 16 interrupts and 3 priority bits (use override_numInterrupts and override_priorityBits parameters to change these).
Thumb-2 instructions are supported.
MPU is present. Use parameter override_MPU_TYPE to disable it or change the number of MPU regions if required.
SysTick timer is present. Use parameter SysTickPresent to disable it if required.
FPU extension is not present. Use parameter override_MVFR0 to enable it if required.
DSP extension is not present. Use parameter override_InstructionAttributes3 to enable it if required.
Bit-band region is present. Use parameter BitBandPresent to disable it if required.
Several parameters can be specified when a processor is instanced in a platform. For this processor instance 'cpu1' it has been instanced with the following parameters:
Table 4: Processor Instance 'cpu1' Parameters (Configurations)
|endian||little||Select processor endian (big or little)|
|simulateexceptions||simulateexceptions||Causes the processor simulate exceptions instead of halting|
|mips||12||The nominal MIPS for the processor|
|semihostvendor||arm.ovpworld.org||The VLNV vendor name of a Semihost library|
|semihostname||armNewlib||The VLNV name of a Semihost library|
Table 5: Processor Instance 'cpu1' Parameters (Attributes)
Memory Map for processor 'cpu1' bus: 'bus1'
Processor instance 'cpu1' is connected to bus 'bus1' using master port 'INSTRUCTION'.
Processor instance 'cpu1' is connected to bus 'bus1' using master port 'DATA'.
Table 6: Memory Map ( 'cpu1' / 'bus1' [width: 32] )
|Lo Address||Hi Address||Instance||Component|
Net Connections to processor: 'cpu1'
Table 7: Processor Net Connections ( 'cpu1' )
Peripheral [ovpworld.org/peripheral/ledRegister/1.0] instance: LEDRegister
Simple test peripheral providing a register that may be used to toggle LED outputs.
Open Source Apache 2.0
This is not based upon a real device
Table 8: Configuration options (attributes) set for instance 'LEDRegister'
Peripheral [ti.ovpworld.org/peripheral/UartInterface/1.0] instance: UART0
UART: Universal Asynchronous Receiver Transmitter This model contains an accurate Register set interface for the TI Stellaris ARM Cortex-M3 based device.
The functionality of this model is limited. Basic status flag setting allows character reception and transmission.
FreeRTOS Cortex-M3 / GCC Port LM3S102 with GCC for Luminary Micros Stellaris microcontrollers http://www.freertos.org/portcortexgcc.html
Open Source Apache 2.0
Table 9: Configuration options (attributes) set for instance 'UART0'