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AtmelParallelIOController



OVP Peripheral Model: AtmelParallelIOController



Model Specific Information

This page provides introductory usage information for an Imperas OVP peripheral behavioral model. The page is split into sections providing specific information for this peripheral, including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.

Description

PIO: Parallel I/O Controller This model contains an accurate Register set interface. The functionality has only been implemented to sufficiently boot uClinux The Parallel I/O Controller has 32 programmable I/O lines. Six pins are dedicated as general-purpose I/O pins. Other I/O lines are multiplexed with an external signal of a peripheral to optimize the use of available package pins. The PIO controller enables generation of an interrupt on input change and insertion of a simple input glitch filter on any of the PIO pins. for more information visit http://www.atmel.com/products/at91

Licensing

Open Source Apache 2.0

Limitations

This model is sufficient to boot Linux

Reference

Rev. 1354D ARM08/02

Location

The ParallelIOController peripheral model is located in an Imperas/OVP installation at the VLNV: atmel.ovpworld.org / peripheral / ParallelIOController / 1.0.



Net Ports

This model has the following net ports:

Table : Net Ports

NameTypeMust Be ConnectedDescription
P0inoutF (False)
P1inoutF (False)
P2inoutF (False)
P3inoutF (False)
P4inoutF (False)
P5inoutF (False)
P6inoutF (False)
P7inoutF (False)
P8inoutF (False)
P9inoutF (False)
P10inoutF (False)
P11inoutF (False)
P12inoutF (False)
P13inoutF (False)
P14inoutF (False)
P15inoutF (False)
P16inoutF (False)
P17inoutF (False)
P18inoutF (False)
P19inoutF (False)
P20inoutF (False)
P21inoutF (False)
P22inoutF (False)
P23inoutF (False)
P24inoutF (False)
P25inoutF (False)
P26inoutF (False)
P27inoutF (False)
P28inoutF (False)
P29inoutF (False)
P30inoutF (False)
P31inoutF (False)
IRQoutputF (False)



Bus Slave Ports

This model has the following bus slave ports:

Bus Slave Port: bp1

Table 1: Bus Slave Port: bp1

NameSize (bytes)Must Be ConnectedDescription
bp10x4000T (True)

Table 2: Bus Slave Port: bp1 Registers:

NameOffsetWidth (bits)DescriptionR/Wis Volatile
REG_PIO_PER0x032
REG_PIO_PDR0x432
REG_PIO_PSR0x832
REG_PIO_OER0x1032
REG_PIO_ODR0x1432
REG_PIO_OSR0x1832
REG_PIO_IFER0x2032
REG_PIO_IFDR0x2432
REG_PIO_IFSR0x2832
REG_PIO_SODR0x3032
REG_PIO_CODR0x3432
REG_PIO_ODSR0x3832
REG_PIO_PDSR0x3c32
REG_PIO_IER0x4032
REG_PIO_IDR0x4432
REG_PIO_IMR0x4832
REG_PIO_ISR0x4c32



Platforms that use this peripheral component

Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.

Table 3: Publicly available platforms using peripheral 'ParallelIOController'

Platform NameVendor
AtmelAT91SAM7atmel.ovpworld.org
AtmelAT91SAM7atmel.ovpworld.org



AtmelPeripherals
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