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FU540



OVP Virtual Platform: FU540

This page provides detailed information about the OVP Virtual Platform Model of the sifive.ovpworld.org FU540 platform.

Licensing

Open Source Apache 2.0

Description

SiFive FU540-C000 SoC module. On start up or reset, the reset code at 0x1004 will jump to a jump table entry indexed by the MSEL register at address 0x1000 (default initial MSEL value is 0xf which will cause a jump to address 0x10000). Use the msel peripheral's MSEL parameter to change the initial value of this register. To run a bare metal application use the --program command line option to specify an elf file to be loaded. It must be linked to use addresses corresponding to the implemented memory regions. The --program option will override the initial pc with the ELF file's start address. To facilitate booting Linux an OVP SmartLoader psuedo-peripheral has been included that provides the functionality of the ZSBL/FSBL. The SmartLoader's dtb parameter should be used to specify the device tree blob file to load, and the bbl elf file should be loaded using the --objfilenoentry command line option.

Reference

SiFive Freedom U540-C000 Manual FU540-C000-v1.0.pdf (https://www.sifive.com/documentation/chips/freedom-u540-c000-manual)

Limitations

Caches and the Cache Controller are not modeled. The Instruction Tightly Integrated Memory (ITIM) is implemented simply as RAM. Deallocation by writing to the byte immediately following the memory is a NOP. The L2 Loosely Integrated Memory (L2-LIM) is implemented simply as RAM. It is always available, since the Cache Controller is not modeled. The L2 Scratchpad memory is not modeled. The Platform DMA Engine (PDMA) is not modeled. The Pulse Width Modulator (PWM) is not modeled. The Inter-Integrated Circuit (I2C) Master Interface is not modeled. The Serial Peripheral Interface (SPI) is not modeled. Instead a Virtio Block MMIO device has been added at reserved address 0x1f000000, using interrupt 54. The General Purpose Input/Output Controller (GPIO) is not modeled. The One-Time Programmable Memory Interface (OTP) is not modeled. DDR controller is not modeled. DDR memory is modeled as RAM. The Debug Interface is not modeled.

Location

The FU540 virtual platform is located in an Imperas/OVP installation at the VLNV: sifive.ovpworld.org / module / FU540 / 1.0.

Platform Summary

Table : Components in platform

TypeInstanceVendorComponent
ProcessorE51_hart0sifive.ovpworld.orgriscvE51
ProcessorU54sifive.ovpworld.orgriscvU54MC
Peripheralmselsifive.ovpworld.orgMSEL
Peripheralclintriscv.ovpworld.orgCLINT
Peripheralplicriscv.ovpworld.orgPLIC
Peripheralprcisifive.ovpworld.orgPRCI
Peripheraluart0sifive.ovpworld.orgUART
Peripheraluart1sifive.ovpworld.orgUART
Peripheralemaccadence.ovpworld.orggem
Peripheralemgmtovpworld.orgdummyPort
Peripheralvbd0ovpworld.orgVirtioBlkMMIO
PeripheralsmartLoaderriscv.ovpworld.orgSmartLoaderRV64Linux
MemorymaskROMovpworld.orgram
Memorymem1ovpworld.orgram
Memorysafe0addrovpworld.orgram
Memoryhart0DTIMovpworld.orgram
Memoryhart0ITIMovpworld.orgram
Memoryhart1ITIMovpworld.orgram
Memoryhart2ITIMovpworld.orgram
Memoryhart3ITIMovpworld.orgram
Memoryhart4ITIMovpworld.orgram
Memoryl2LIMovpworld.orgram
Busbus0(builtin)address width:38

Platform Simulation Attributes

Table 1: Platform Simulation Attributes

AttributeValueDescription
stoponctrlcstoponctrlcStop on control-C



External Ports for Module FU540

Table 2: External Ports

Port TypePort NameInternal Connection
netportgi1gi1
netportgi2gi2
netportgi3gi3
netportgi4gi4
netportgi5gi5
netportgi6gi6
netportgi7gi7
netportgi8gi8
netportgi9gi9
netportgi10gi10
netportgi11gi11
netportgi12gi12
netportgi13gi13
netportgi14gi14
netportgi15gi15
netportgi16gi16
netportgi17gi17
netportgi18gi18
netportgi19gi19
netportgi20gi20
netportgi21gi21
netportgi22gi22
netportgi23gi23
netportgi24gi24
netportgi25gi25
netportgi26gi26
netportgi27gi27
netportgi28gi28
netportgi29gi29
netportgi30gi30
netportgi31gi31
netportgi32gi32
netportgi33gi33
netportgi34gi34
netportgi35gi35
netportgi36gi36
netportgi37gi37
netportgi38gi38
netportgi39gi39
netportgi40gi40
netportgi41gi41
netportgi42gi42
netportgi43gi43
netportgi44gi44
netportgi45gi45
netportgi46gi46
netportgi47gi47
netportgi48gi48
netportgi49gi49
netportgi50gi50
netportgi51gi51
netportgi52gi52
netportgi53gi53



Processor [sifive.ovpworld.org/processor/riscv/1.0] instance: E51_hart0

Processor model type: 'riscv' variant 'E51' definition

Imperas OVP processor models support multiple variants and details of the variants implemented in this model can be found in:
- the Imperas installation located at ImperasLib/source/sifive.ovpworld.org/processor/riscv/1.0/doc
- the OVP website: OVP_Model_Specific_Information_sifive_riscv_E51.pdf

Description

RISC-V E51 64-bit processor model

Licensing

This Model is released under the Open Source Apache 2.0

Features

The model supports the following architectural features, defined in the misa CSR:
extension A (atomic instructions)
extension C (compressed instructions)
RV32I/64I/128I base ISA
extension M (integer multiply/divide instructions)
extension U (User mode)
64-bit XLEN
If required, supported architectural features may be overridden using parameter "misa_Extensions". Parameter "misa_Extensions_mask" can be used to specify which features can be dynamically enabled or disabled by writes to the misa register.
On this variant, the Machine trap-vector base-address register (mtvec) is writable. It can instead be configured as read-only using parameter "mtvec_is_ro".
Values written to "mtvec" are masked using the value 0x3ffffffffd. A different mask of writable bits may be specified using parameter "mtvec_mask" if required. In addition, when Vectored interrupt mode is enabled, parameter "tvec_align" may be used to specify additional hardware-enforced base address alignment. In this variant, "tvec_align" defaults to 64.
The initial value of "mtvec" is 0x0. A different value may be specified using parameter "mtvec" if required.
On reset, the model will restart at address 0x0. A different reset address may be specified using parameter "reset_address" if required.
On an NMI, the model will restart at address 0x0. A different NMI address may be specified using parameter "nmi_address" if required.
WFI will halt the processor until an interrupt occurs. It can instead be configured as a NOP using parameter "wfi_is_nop". WFI timeout wait is implemented with a time limit of 0 (i.e. WFI causes an Illegal Instruction trap in Supervisor mode when mstatus.TW=1).
The "cycle" CSR is implemented in this variant. Set parameter "cycle_undefined" to True to instead specify that "cycle" is unimplemented and reads of it should trap to Machine mode.
The "time" CSR is not implemented in this variant and reads of it will require emulation in Machine mode. Set parameter "time_undefined" to False to instead specify that "time" is implemented.
The "instret" CSR is implemented in this variant. Set parameter "instret_undefined" to True to instead specify that "instret" is unimplemented and reads of it should trap to Machine mode.
Unaligned memory accesses are not supported by this variant. Set parameter "unaligned" to "T" to enable such accesses.
8 PMP entries are implemented by this variant. Use parameter "PMP_registers" to specify a different number of PMP entries; set the parameter to 0 to disable the PMP unit. The PMP grain size (G) is 0, meaning that PMP regions as small as 4 bytes are implemented. Use parameter "PMP_grain" to specify a different grain size if required.
LR/SC instructions are implemented with a 64-byte reservation granule. A different granule size may be specified using parameter "lr_sc_grain".

Interrupts

The "reset" port is an active-high reset input. The processor is halted when "reset" goes high and resumes execution from the reset address specified using the "reset_address" parameter when the signal goes low. The "mcause" register is cleared to zero.
The "nmi" port is an active-high NMI input. The processor is halted when "nmi" goes high and resumes execution from the address specified using the "nmi_address" parameter when the signal goes low. The "mcause" register is cleared to zero.
All other interrupt ports are active high.

Debug Mask

It is possible to enable model debug messages in various categories. This can be done statically using the "override_debugMask" parameter, or dynamically using the "debugflags" command. Enabled messages are specified using a bitmask value, as follows:
Value 0x002: enable debugging of PMP and virtual memory state;
Value 0x004: enable debugging of interrupt state.
All other bits in the debug bitmask are reserved and must not be set to non-zero values.

Integration Support

This model implements a number of non-architectural pseudo-registers and other features to facilitate integration.

CSR Register External Implementation

If parameter "enable_CSR_bus" is True, an artifact 16-bit bus "CSR" is enabled. Slave callbacks installed on this bus can be used to implement modified CSR behavior (use opBusSlaveNew or icmMapExternalMemory, depending on the client API). A CSR with index 0xABC is mapped on the bus at address 0xABC0; as a concrete example, implementing CSR "time" (number 0xC01) externally requires installation of callbacks at address 0xC010 on the CSR bus.

LR/SC Active Address

Artifact register "LRSCAddress" shows the active LR/SC lock address. The register holds all-ones if there is no LR/SC operation active.

Limitations

Instruction pipelines are not modeled in any way. All instructions are assumed to complete immediately. This means that instruction barrier instructions (e.g. fence.i) are treated as NOPs, with the exception of any Illegal Instruction behavior, which is modeled.
Caches and write buffers are not modeled in any way. All loads, fetches and stores complete immediately and in order, and are fully synchronous. Data barrier instructions (e.g. fence) are treated as NOPs, with the exception of any Illegal Instruction behavior, which is modeled.
Real-world timing effects are not modeled: all instructions are assumed to complete in a single cycle.
Hardware Performance Monitor and Debug registers are not implemented and hardwired to zero.

Verification

All instructions have been extensively tested by Imperas, using tests generated specifically for this model and also reference tests from https://github.com/riscv/riscv-tests.

References

The Model details are based upon the following specifications:
---- RISC-V Instruction Set Manual, Volume I: User-Level ISA (User Architecture Version 2.3-draft)
---- RISC-V Instruction Set Manual, Volume II: Privileged Architecture (Privileged Architecture Version 1.11-draft)
---- SiFive E51 Core Complex Manual v1p2

Instance Parameters

Several parameters can be specified when a processor is instanced in a platform. For this processor instance 'E51_hart0' it has been instanced with the following parameters:

Table 3: Processor Instance 'E51_hart0' Parameters (Configurations)

ParameterValueDescription
simulateexceptionssimulateexceptionsCauses the processor simulate exceptions instead of halting
mips1000The nominal MIPS for the processor

Table 4: Processor Instance 'E51_hart0' Parameters (Attributes)

Parameter NameValueType
mhartid0Uns64
local_int_num48Uns32
reset_address0x1004Uns64
variantE51enum

Memory Map for processor 'E51_hart0' bus: 'bus0'

Processor instance 'E51_hart0' is connected to bus 'bus0' using master port 'INSTRUCTION'.

Processor instance 'E51_hart0' is connected to bus 'bus0' using master port 'DATA'.

Table 5: Memory Map ( 'E51_hart0' / 'bus0' [width: 38] )

Lo AddressHi AddressInstanceComponent
0x00xFFsafe0addrram
0x10000x1FFFmselMSEL
0x100000x17FFFmaskROMram
0x10000000x1001FFFhart0DTIMram
0x18000000x1802000hart0ITIMram
0x18080000x180F000hart1ITIMram
0x18100000x1817000hart2ITIMram
0x18180000x181F000hart3ITIMram
0x18200000x1827000hart4ITIMram
0x20000000x200BFFFclintCLINT
0x80000000x9FFFFFFl2LIMram
0xC0000000xFFFFFFFplicPLIC
0x100000000x10000FFFprciPRCI
0x100100000x1001001Buart0UART
0x100110000x1001101Buart1UART
0x100900000x10090FFFemacgem
0x100A00000x100A0FFFemgmtdummyPort
0x1F0000000x1F0001FFvbd0VirtioBlkMMIO
0x800000000xBFFFFFFFmem1ram

Net Connections to processor: 'E51_hart0'

Table 6: Processor Net Connections ( 'E51_hart0' )

Net PortNetInstanceComponent
MTimerInterruptMTimerInterrupt0clintCLINT
MSWInterruptMSWInterrupt0clintCLINT
MExternalInterruptirqT0plicPLIC



Processor [sifive.ovpworld.org/processor/riscv/1.0] instance: U54

Processor model type: 'riscv' variant 'U54MC' definition

Imperas OVP processor models support multiple variants and details of the variants implemented in this model can be found in:
- the Imperas installation located at ImperasLib/source/sifive.ovpworld.org/processor/riscv/1.0/doc
- the OVP website: OVP_Model_Specific_Information_sifive_riscv_U54MC.pdf

Instance Parameters

Several parameters can be specified when a processor is instanced in a platform. For this processor instance 'U54' it has been instanced with the following parameters:

Table 7: Processor Instance 'U54' Parameters (Configurations)

ParameterValueDescription
simulateexceptionssimulateexceptionsCauses the processor simulate exceptions instead of halting
mips1000The nominal MIPS for the processor

Table 8: Processor Instance 'U54' Parameters (Attributes)

Parameter NameValueType
mhartid1Uns64
local_int_num48Uns32
reset_address0x1004Uns64
numHarts4Uns32
variantU54MCenum

Memory Map for processor 'U54' bus: 'bus0'

Processor instance 'U54' is connected to bus 'bus0' using master port 'INSTRUCTION'.

Processor instance 'U54' is connected to bus 'bus0' using master port 'DATA'.

Table 9: Memory Map ( 'U54' / 'bus0' [width: 38] )

Lo AddressHi AddressInstanceComponent
0x00xFFsafe0addrram
0x10000x1FFFmselMSEL
0x100000x17FFFmaskROMram
0x10000000x1001FFFhart0DTIMram
0x18000000x1802000hart0ITIMram
0x18080000x180F000hart1ITIMram
0x18100000x1817000hart2ITIMram
0x18180000x181F000hart3ITIMram
0x18200000x1827000hart4ITIMram
0x20000000x200BFFFclintCLINT
0x80000000x9FFFFFFl2LIMram
0xC0000000xFFFFFFFplicPLIC
0x100000000x10000FFFprciPRCI
0x100100000x1001001Buart0UART
0x100110000x1001101Buart1UART
0x100900000x10090FFFemacgem
0x100A00000x100A0FFFemgmtdummyPort
0x1F0000000x1F0001FFvbd0VirtioBlkMMIO
0x800000000xBFFFFFFFmem1ram

Net Connections to processor: 'U54'

Table 10: Processor Net Connections ( 'U54' )

Net PortNetInstanceComponent
hart1_MTimerInterruptMTimerInterrupt1clintCLINT
hart1_MSWInterruptMSWInterrupt1clintCLINT
hart1_MExternalInterruptirqT1plicPLIC
hart1_SExternalInterruptirqT2plicPLIC
hart2_MTimerInterruptMTimerInterrupt2clintCLINT
hart2_MSWInterruptMSWInterrupt2clintCLINT
hart2_MExternalInterruptirqT3plicPLIC
hart2_SExternalInterruptirqT4plicPLIC
hart3_MTimerInterruptMTimerInterrupt3clintCLINT
hart3_MSWInterruptMSWInterrupt3clintCLINT
hart3_MExternalInterruptirqT5plicPLIC
hart3_SExternalInterruptirqT6plicPLIC
hart4_MTimerInterruptMTimerInterrupt4clintCLINT
hart4_MSWInterruptMSWInterrupt4clintCLINT
hart4_MExternalInterruptirqT7plicPLIC
hart4_SExternalInterruptirqT8plicPLIC



Peripheral Instances



Peripheral [sifive.ovpworld.org/peripheral/MSEL/1.0] instance: msel

Description

Mode Select reset module. Entered on reset and calls boot code based on MSEL pin state. Override the MSEL parameter to specify the initial value for the MSEL pin state (default 0xf). From application code or debugger write to the MSEL register at offset 0 to change the MSEL pin state.

Limitations

None

Licensing

Open Source Apache 2.0

Reference

SiFive Freedom U540-C000 Manual FU540-C000-v1.0.pdf (https://www.sifive.com/documentation/chips/freedom-u540-c000-manual)

There are no configuration options set for this peripheral instance.



Peripheral [riscv.ovpworld.org/peripheral/CLINT/1.0] instance: clint

Licensing

Open Source Apache 2.0

Description

Risc-V Core Local Interruptor (CLINT). Use the num_harts parameter to specify the number of harts suported (default 1). For each supported hart there will be an MTimerInterruptN and MSWInterruptN net port, plus msipN and mtimecmpN registers implemented, where N is a value from 0..num_harts-1 There is also a single mtime register.

Limitations

Writes to mtime register are not supported

Reference

SiFive Freedom U540-C000 Manual FU540-C000-v1.0.pdf (https://www.sifive.com/documentation/chips/freedom-u540-c000-manual)

Table 11: Configuration options (attributes) set for instance 'clint'

AttributesValue
num_harts5
clockMHz1.0



Peripheral [riscv.ovpworld.org/peripheral/PLIC/1.0] instance: plic

Licensing

Open Source Apache 2.0

Description

PLIC Interrupt Controller

Limitations

Sufficient functionality to boot Virtio BusyBear Linux Kernel. The num_priorities parameter is currently ignored. All 32 bits of priority registers are supported.

Reference

The RISC-V Instruction Set Manual Volume II: Privileged Architecture Version 1.10 (https://riscv.org/specifications/privileged-isa)
SiFive Freedom U540-C000 Manual FU540-C000-v1.0.pdf (https://www.sifive.com/documentation/chips/freedom-u540-c000-manual)

Table 12: Configuration options (attributes) set for instance 'plic'

AttributesValue
num_targets9
num_sources53



Peripheral [sifive.ovpworld.org/peripheral/PRCI/1.0] instance: prci

Description

Power Reset Clocking Interrupt (PRCI) block for SiFive FU540 chip

Limitations

None
Register only model. Reset values based on typical post-ZSBL configuration (1GHz coreclk, 500MHz tlclk).

Licensing

Open Source Apache 2.0

Reference

SiFive Freedom U540-C000 Manual FU540-C000-v1.0.pdf (https://www.sifive.com/documentation/chips/freedom-u540-c000-manual)

There are no configuration options set for this peripheral instance.



Peripheral [sifive.ovpworld.org/peripheral/UART/1.0] instance: uart0

Licensing

Open Source Apache 2.0

Description

Sifive UART

Limitations

When simulatebaud parameter is set to true baud rate delays are modeled for receive only, not transmit. Data always sent immediately.

Reference

SiFive Freedom U540-C000 Manual FU540-C000-v1.0.pdf (https://www.sifive.com/documentation/chips/freedom-u540-c000-manual)

Table 13: Configuration options (attributes) set for instance 'uart0'

AttributesValue
refClkFreq500000000



Peripheral [sifive.ovpworld.org/peripheral/UART/1.0] instance: uart1

Licensing

Open Source Apache 2.0

Description

Sifive UART

Limitations

When simulatebaud parameter is set to true baud rate delays are modeled for receive only, not transmit. Data always sent immediately.

Reference

SiFive Freedom U540-C000 Manual FU540-C000-v1.0.pdf (https://www.sifive.com/documentation/chips/freedom-u540-c000-manual)

Table 14: Configuration options (attributes) set for instance 'uart1'

AttributesValue
refClkFreq500000000



Peripheral [cadence.ovpworld.org/peripheral/gem/1.0] instance: emac

Description

Model of Cadence Gigabit Ethernet Controller (GEM). For further details please consult README-EMAC.txt
This model is based upon the data and use in the Xilinx Zynq
Basic network Tx/Rx functionality tested using Xilinx Linux Kernel using wget and other similar tools
Tested with Xilinx SDK Example driver.

Licensing

Open Source Apache 2.0

Limitations

This model is based upon the data from the Xilinx Zynq platform, other registers may not be included.
Does not implement: VLAN, pause frames, filtering or timestamps.

Reference

Zynq-7000 TRM (https://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf)

There are no configuration options set for this peripheral instance.



Peripheral [ovpworld.org/peripheral/dummyPort/1.0] instance: emgmt

Description

Dummy peripheral that provides an area for accesses.

Limitations

Has no behavior. This peripheral defines a port through which a 4k byte memory area can be read and written.

Licensing

Open Source Apache 2.0

Reference

This is not based upon a real device

There are no configuration options set for this peripheral instance.



Peripheral [ovpworld.org/peripheral/VirtioBlkMMIO/1.0] instance: vbd0

Description

VIRTIO version 1 mmio block device This model implements a VIRTIO MMIO block device as described in: http://docs.oasis-open.org/virtio/virtio/v1.0/virtio-v1.0.pdf. Use the VB_DRIVE parameter to specify the disk image file to use. Set the VB_DRIVE_DELTA parameter to 1 to prevent writes to disk during simulation from changing the image file.

Limitations

Only supports the Legacy (Device Version 1) interface. Only little endian guests are supported.

Licensing

Open Source Apache 2.0

Reference

http://docs.oasis-open.org/virtio/virtio/v1.0/virtio-v1.0.pdf

There are no configuration options set for this peripheral instance.



Peripheral [riscv.ovpworld.org/peripheral/SmartLoaderRV64Linux/1.0] instance: smartLoader

Licensing

Open Source Apache 2.0

Description

Psuedo-peripheral to insert boot code for a Riscv 64-bit Linux kernel boot. Loads simulated memory with a device tree blob file and boot code to set regs and jump to a Risc-v Linux Kernel.

Limitations

Only supports little endian

Reference

RISC-V Linux Kernel development

Table 15: Configuration options (attributes) set for instance 'smartLoader'

AttributesValue
bootaddr0x80000000
slbootaddr0x10000
membase0x80000000
memsize0x40000000



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