Name | Type | Must Be Connected | Description |
---|---|---|---|
Reset | input | F (False) |
Table : Net Ports
Name | Type | Must Be Connected | Description |
---|---|---|---|
Reset | input | F (False) |
Table 1: Bus Slave Port: bport1
Name | Size (bytes) | Must Be Connected | Description |
---|---|---|---|
bport1 | 0x1000 | F (False) |
Table 2: Bus Slave Port: bport1 Registers:
Name | Offset | Width (bits) | Description | R/W | is Volatile |
---|---|---|---|---|---|
ab_DAT0L | 0x0 | 8 | DAC Data Low Register, array offset: 0x0, array step: 0x2 | ||
ab_DAT0H | 0x1 | 8 | DAC Data High Register, array offset: 0x1, array step: 0x2 | ||
ab_DAT1L | 0x2 | 8 | DAC Data Low Register, array offset: 0x0, array step: 0x2 | ||
ab_DAT1H | 0x3 | 8 | DAC Data High Register, array offset: 0x1, array step: 0x2 | ||
ab_DAT2L | 0x4 | 8 | DAC Data Low Register, array offset: 0x0, array step: 0x2 | ||
ab_DAT2H | 0x5 | 8 | DAC Data High Register, array offset: 0x1, array step: 0x2 | ||
ab_DAT3L | 0x6 | 8 | DAC Data Low Register, array offset: 0x0, array step: 0x2 | ||
ab_DAT3H | 0x7 | 8 | DAC Data High Register, array offset: 0x1, array step: 0x2 | ||
ab_DAT4L | 0x8 | 8 | DAC Data Low Register, array offset: 0x0, array step: 0x2 | ||
ab_DAT4H | 0x9 | 8 | DAC Data High Register, array offset: 0x1, array step: 0x2 | ||
ab_DAT5L | 0xa | 8 | DAC Data Low Register, array offset: 0x0, array step: 0x2 | ||
ab_DAT5H | 0xb | 8 | DAC Data High Register, array offset: 0x1, array step: 0x2 | ||
ab_DAT6L | 0xc | 8 | DAC Data Low Register, array offset: 0x0, array step: 0x2 | ||
ab_DAT6H | 0xd | 8 | DAC Data High Register, array offset: 0x1, array step: 0x2 | ||
ab_DAT7L | 0xe | 8 | DAC Data Low Register, array offset: 0x0, array step: 0x2 | ||
ab_DAT7H | 0xf | 8 | DAC Data High Register, array offset: 0x1, array step: 0x2 | ||
ab_DAT8L | 0x10 | 8 | DAC Data Low Register, array offset: 0x0, array step: 0x2 | ||
ab_DAT8H | 0x11 | 8 | DAC Data High Register, array offset: 0x1, array step: 0x2 | ||
ab_DAT9L | 0x12 | 8 | DAC Data Low Register, array offset: 0x0, array step: 0x2 | ||
ab_DAT9H | 0x13 | 8 | DAC Data High Register, array offset: 0x1, array step: 0x2 | ||
ab_DAT10L | 0x14 | 8 | DAC Data Low Register, array offset: 0x0, array step: 0x2 | ||
ab_DAT10H | 0x15 | 8 | DAC Data High Register, array offset: 0x1, array step: 0x2 | ||
ab_DAT11L | 0x16 | 8 | DAC Data Low Register, array offset: 0x0, array step: 0x2 | ||
ab_DAT11H | 0x17 | 8 | DAC Data High Register, array offset: 0x1, array step: 0x2 | ||
ab_DAT12L | 0x18 | 8 | DAC Data Low Register, array offset: 0x0, array step: 0x2 | ||
ab_DAT12H | 0x19 | 8 | DAC Data High Register, array offset: 0x1, array step: 0x2 | ||
ab_DAT13L | 0x1a | 8 | DAC Data Low Register, array offset: 0x0, array step: 0x2 | ||
ab_DAT13H | 0x1b | 8 | DAC Data High Register, array offset: 0x1, array step: 0x2 | ||
ab_DAT14L | 0x1c | 8 | DAC Data Low Register, array offset: 0x0, array step: 0x2 | ||
ab_DAT14H | 0x1d | 8 | DAC Data High Register, array offset: 0x1, array step: 0x2 | ||
ab_DAT15L | 0x1e | 8 | DAC Data Low Register, array offset: 0x0, array step: 0x2 | ||
ab_DAT15H | 0x1f | 8 | DAC Data High Register, array offset: 0x1, array step: 0x2 | ||
ab_SR | 0x20 | 8 | DAC Status Register, offset: 0x20 | ||
ab_C0 | 0x21 | 8 | DAC Control Register, offset: 0x21 | ||
ab_C1 | 0x22 | 8 | DAC Control Register 1, offset: 0x22 | ||
ab_C2 | 0x23 | 8 | DAC Control Register 2, offset: 0x23 |
Table 3: Publicly available platforms using peripheral 'KinetisDAC'