Name | Type | Must Be Connected | Description |
---|---|---|---|
Reset | input | F (False) |
Table : Net Ports
Name | Type | Must Be Connected | Description |
---|---|---|---|
Reset | input | F (False) |
Table 1: Bus Slave Port: bport1
Name | Size (bytes) | Must Be Connected | Description |
---|---|---|---|
bport1 | 0x1000 | F (False) |
Table 2: Bus Slave Port: bport1 Registers:
Name | Offset | Width (bits) | Description | R/W | is Volatile |
---|---|---|---|---|---|
ab_CR00 | 0x0 | 32 | DDR Control Register 0, offset: 0x0 | ||
ab_CR01 | 0x4 | 32 | DDR Control Register 1, offset: 0x4 | ||
ab_CR02 | 0x8 | 32 | DDR Control Register 2, offset: 0x8 | ||
ab_CR03 | 0xc | 32 | DDR Control Register 3, offset: 0xC | ||
ab_CR04 | 0x10 | 32 | DDR Control Register 4, offset: 0x10 | ||
ab_CR05 | 0x14 | 32 | DDR Control Register 5, offset: 0x14 | ||
ab_CR06 | 0x18 | 32 | DDR Control Register 6, offset: 0x18 | ||
ab_CR07 | 0x1c | 32 | DDR Control Register 7, offset: 0x1C | ||
ab_CR08 | 0x20 | 32 | DDR Control Register 8, offset: 0x20 | ||
ab_CR09 | 0x24 | 32 | DDR Control Register 9, offset: 0x24 | ||
ab_CR10 | 0x28 | 32 | DDR Control Register 10, offset: 0x28 | ||
ab_CR11 | 0x2c | 32 | DDR Control Register 11, offset: 0x2C | ||
ab_CR12 | 0x30 | 32 | DDR Control Register 12, offset: 0x30 | ||
ab_CR13 | 0x34 | 32 | DDR Control Register 13, offset: 0x34 | ||
ab_CR14 | 0x38 | 32 | DDR Control Register 14, offset: 0x38 | ||
ab_CR15 | 0x3c | 32 | DDR Control Register 15, offset: 0x3C | ||
ab_CR16 | 0x40 | 32 | DDR Control Register 16, offset: 0x40 | ||
ab_CR17 | 0x44 | 32 | DDR Control Register 17, offset: 0x44 | ||
ab_CR18 | 0x48 | 32 | DDR Control Register 18, offset: 0x48 | ||
ab_CR19 | 0x4c | 32 | DDR Control Register 19, offset: 0x4C | ||
ab_CR20 | 0x50 | 32 | DDR Control Register 20, offset: 0x50 | ||
ab_CR21 | 0x54 | 32 | DDR Control Register 21, offset: 0x54 | ||
ab_CR22 | 0x58 | 32 | DDR Control Register 22, offset: 0x58 | ||
ab_CR23 | 0x5c | 32 | DDR Control Register 23, offset: 0x5C | ||
ab_CR24 | 0x60 | 32 | DDR Control Register 24, offset: 0x60 | ||
ab_CR25 | 0x64 | 32 | DDR Control Register 25, offset: 0x64 | ||
ab_CR26 | 0x68 | 32 | DDR Control Register 26, offset: 0x68 | ||
ab_CR27 | 0x6c | 32 | DDR Control Register 27, offset: 0x6C | ||
ab_CR28 | 0x70 | 32 | DDR Control Register 28, offset: 0x70 | ||
ab_CR29 | 0x74 | 32 | DDR Control Register 29, offset: 0x74 | ||
ab_CR30 | 0x78 | 32 | DDR Control Register 30, offset: 0x78 | ||
ab_CR31 | 0x7c | 32 | DDR Control Register 31, offset: 0x7C | ||
ab_CR32 | 0x80 | 32 | DDR Control Register 32, offset: 0x80 | ||
ab_CR33 | 0x84 | 32 | DDR Control Register 33, offset: 0x84 | ||
ab_CR34 | 0x88 | 32 | DDR Control Register 34, offset: 0x88 | ||
ab_CR35 | 0x8c | 32 | DDR Control Register 35, offset: 0x8C | ||
ab_CR36 | 0x90 | 32 | DDR Control Register 36, offset: 0x90 | ||
ab_CR37 | 0x94 | 32 | DDR Control Register 37, offset: 0x94 | ||
ab_CR38 | 0x98 | 32 | DDR Control Register 38, offset: 0x98 | ||
ab_CR39 | 0x9c | 32 | DDR Control Register 39, offset: 0x9C | ||
ab_CR40 | 0xa0 | 32 | DDR Control Register 40, offset: 0xA0 | ||
ab_CR41 | 0xa4 | 32 | DDR Control Register 41, offset: 0xA4 | ||
ab_CR42 | 0xa8 | 32 | DDR Control Register 42, offset: 0xA8 | ||
ab_CR43 | 0xac | 32 | DDR Control Register 43, offset: 0xAC | ||
ab_CR44 | 0xb0 | 32 | DDR Control Register 44, offset: 0xB0 | ||
ab_CR45 | 0xb4 | 32 | DDR Control Register 45, offset: 0xB4 | ||
ab_CR46 | 0xb8 | 32 | DDR Control Register 46, offset: 0xB8 | ||
ab_CR47 | 0xbc | 32 | DDR Control Register 47, offset: 0xBC | ||
ab_CR48 | 0xc0 | 32 | DDR Control Register 48, offset: 0xC0 | ||
ab_CR49 | 0xc4 | 32 | DDR Control Register 49, offset: 0xC4 | ||
ab_CR50 | 0xc8 | 32 | DDR Control Register 50, offset: 0xC8 | ||
ab_CR51 | 0xcc | 32 | DDR Control Register 51, offset: 0xCC | ||
ab_CR52 | 0xd0 | 32 | DDR Control Register 52, offset: 0xD0 | ||
ab_CR53 | 0xd4 | 32 | DDR Control Register 53, offset: 0xD4 | ||
ab_CR54 | 0xd8 | 32 | DDR Control Register 54, offset: 0xD8 | ||
ab_CR55 | 0xdc | 32 | DDR Control Register 55, offset: 0xDC | ||
ab_CR56 | 0xe0 | 32 | DDR Control Register 56, offset: 0xE0 | ||
ab_CR57 | 0xe4 | 32 | DDR Control Register 57, offset: 0xE4 | ||
ab_CR58 | 0xe8 | 32 | DDR Control Register 58, offset: 0xE8 | ||
ab_CR59 | 0xec | 32 | DDR Control Register 59, offset: 0xEC | ||
ab_CR60 | 0xf0 | 32 | DDR Control Register 60, offset: 0xF0 | ||
ab_CR61 | 0xf4 | 32 | DDR Control Register 61, offset: 0xF4 | ||
ab_CR62 | 0xf8 | 32 | DDR Control Register 62, offset: 0xF8 | ||
ab_CR63 | 0xfc | 32 | DDR Control Register 63, offset: 0xFC | ||
ab_RCR | 0x180 | 32 | RCR Control Register, offset: 0x180 |
Table 3: Publicly available platforms using peripheral 'KinetisDDR'