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FreescaleKinetisDDR



OVP Peripheral Model: FreescaleKinetisDDR



Model Specific Information

This page provides introductory usage information for an Imperas OVP peripheral behavioral model. The page is split into sections providing specific information for this peripheral, including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.

Description

Model of the DDR peripheral used on the Freescale Kinetis platform

Limitations

Provides the base behaviour for the OVP Freescale Kinetis platforms

Reference

www.freescale.com/Kinetis

Licensing

Open Source Apache 2.0

Location

The KinetisDDR peripheral model is located in an Imperas/OVP installation at the VLNV: freescale.ovpworld.org / peripheral / KinetisDDR / 1.0.



Net Ports

This model has the following net ports:

Table : Net Ports

NameTypeMust Be ConnectedDescription
ResetinputF (False)



Bus Slave Ports

This model has the following bus slave ports:

Bus Slave Port: bport1

Table 1: Bus Slave Port: bport1

NameSize (bytes)Must Be ConnectedDescription
bport10x1000F (False)

Table 2: Bus Slave Port: bport1 Registers:

NameOffsetWidth (bits)DescriptionR/Wis Volatile
ab_CR000x032DDR Control Register 0, offset: 0x0
ab_CR010x432DDR Control Register 1, offset: 0x4
ab_CR020x832DDR Control Register 2, offset: 0x8
ab_CR030xc32DDR Control Register 3, offset: 0xC
ab_CR040x1032DDR Control Register 4, offset: 0x10
ab_CR050x1432DDR Control Register 5, offset: 0x14
ab_CR060x1832DDR Control Register 6, offset: 0x18
ab_CR070x1c32DDR Control Register 7, offset: 0x1C
ab_CR080x2032DDR Control Register 8, offset: 0x20
ab_CR090x2432DDR Control Register 9, offset: 0x24
ab_CR100x2832DDR Control Register 10, offset: 0x28
ab_CR110x2c32DDR Control Register 11, offset: 0x2C
ab_CR120x3032DDR Control Register 12, offset: 0x30
ab_CR130x3432DDR Control Register 13, offset: 0x34
ab_CR140x3832DDR Control Register 14, offset: 0x38
ab_CR150x3c32DDR Control Register 15, offset: 0x3C
ab_CR160x4032DDR Control Register 16, offset: 0x40
ab_CR170x4432DDR Control Register 17, offset: 0x44
ab_CR180x4832DDR Control Register 18, offset: 0x48
ab_CR190x4c32DDR Control Register 19, offset: 0x4C
ab_CR200x5032DDR Control Register 20, offset: 0x50
ab_CR210x5432DDR Control Register 21, offset: 0x54
ab_CR220x5832DDR Control Register 22, offset: 0x58
ab_CR230x5c32DDR Control Register 23, offset: 0x5C
ab_CR240x6032DDR Control Register 24, offset: 0x60
ab_CR250x6432DDR Control Register 25, offset: 0x64
ab_CR260x6832DDR Control Register 26, offset: 0x68
ab_CR270x6c32DDR Control Register 27, offset: 0x6C
ab_CR280x7032DDR Control Register 28, offset: 0x70
ab_CR290x7432DDR Control Register 29, offset: 0x74
ab_CR300x7832DDR Control Register 30, offset: 0x78
ab_CR310x7c32DDR Control Register 31, offset: 0x7C
ab_CR320x8032DDR Control Register 32, offset: 0x80
ab_CR330x8432DDR Control Register 33, offset: 0x84
ab_CR340x8832DDR Control Register 34, offset: 0x88
ab_CR350x8c32DDR Control Register 35, offset: 0x8C
ab_CR360x9032DDR Control Register 36, offset: 0x90
ab_CR370x9432DDR Control Register 37, offset: 0x94
ab_CR380x9832DDR Control Register 38, offset: 0x98
ab_CR390x9c32DDR Control Register 39, offset: 0x9C
ab_CR400xa032DDR Control Register 40, offset: 0xA0
ab_CR410xa432DDR Control Register 41, offset: 0xA4
ab_CR420xa832DDR Control Register 42, offset: 0xA8
ab_CR430xac32DDR Control Register 43, offset: 0xAC
ab_CR440xb032DDR Control Register 44, offset: 0xB0
ab_CR450xb432DDR Control Register 45, offset: 0xB4
ab_CR460xb832DDR Control Register 46, offset: 0xB8
ab_CR470xbc32DDR Control Register 47, offset: 0xBC
ab_CR480xc032DDR Control Register 48, offset: 0xC0
ab_CR490xc432DDR Control Register 49, offset: 0xC4
ab_CR500xc832DDR Control Register 50, offset: 0xC8
ab_CR510xcc32DDR Control Register 51, offset: 0xCC
ab_CR520xd032DDR Control Register 52, offset: 0xD0
ab_CR530xd432DDR Control Register 53, offset: 0xD4
ab_CR540xd832DDR Control Register 54, offset: 0xD8
ab_CR550xdc32DDR Control Register 55, offset: 0xDC
ab_CR560xe032DDR Control Register 56, offset: 0xE0
ab_CR570xe432DDR Control Register 57, offset: 0xE4
ab_CR580xe832DDR Control Register 58, offset: 0xE8
ab_CR590xec32DDR Control Register 59, offset: 0xEC
ab_CR600xf032DDR Control Register 60, offset: 0xF0
ab_CR610xf432DDR Control Register 61, offset: 0xF4
ab_CR620xf832DDR Control Register 62, offset: 0xF8
ab_CR630xfc32DDR Control Register 63, offset: 0xFC
ab_RCR0x18032RCR Control Register, offset: 0x180



Platforms that use this peripheral component

Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.

Table 3: Publicly available platforms using peripheral 'KinetisDDR'

Platform NameVendor
FreescaleKinetis60freescale.ovpworld.org
FreescaleKinetis64freescale.ovpworld.org



FreescalePeripherals
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