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FreescaleKinetisDMA



OVP Peripheral Model: FreescaleKinetisDMA



Model Specific Information

This page provides introductory usage information for an Imperas OVP peripheral behavioral model. The page is split into sections providing specific information for this peripheral, including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.

Description

Model of the DMA peripheral used on the Freescale Kinetis platform

Limitations

Provides the base behaviour for the OVP Freescale Kinetis platforms

Reference

www.freescale.com/Kinetis

Licensing

Open Source Apache 2.0

Location

The KinetisDMA peripheral model is located in an Imperas/OVP installation at the VLNV: freescale.ovpworld.org / peripheral / KinetisDMA / 1.0.



Net Ports

This model has the following net ports:

Table : Net Ports

NameTypeMust Be ConnectedDescription
ResetinputF (False)
eDMARequestinputF (False)
eDMADoneoutputF (False)
errorInterruptoutputF (False)DMA Error Interrupt port
dmaInterrupt_ch0outputF (False)DMA Done for channel 0 Interrupt port
dmaInterrupt_ch1outputF (False)DMA Done for channel 1 Interrupt port
dmaInterrupt_ch2outputF (False)DMA Done for channel 2 Interrupt port
dmaInterrupt_ch3outputF (False)DMA Done for channel 3 Interrupt port
dmaInterrupt_ch4outputF (False)DMA Done for channel 4 Interrupt port
dmaInterrupt_ch5outputF (False)DMA Done for channel 5 Interrupt port
dmaInterrupt_ch6outputF (False)DMA Done for channel 6 Interrupt port
dmaInterrupt_ch7outputF (False)DMA Done for channel 7 Interrupt port
dmaInterrupt_ch8outputF (False)DMA Done for channel 8 Interrupt port
dmaInterrupt_ch9outputF (False)DMA Done for channel 9 Interrupt port
dmaInterrupt_ch10outputF (False)DMA Done for channel 10 Interrupt port
dmaInterrupt_ch11outputF (False)DMA Done for channel 11 Interrupt port
dmaInterrupt_ch12outputF (False)DMA Done for channel 12 Interrupt port
dmaInterrupt_ch13outputF (False)DMA Done for channel 13 Interrupt port
dmaInterrupt_ch14outputF (False)DMA Done for channel 14 Interrupt port
dmaInterrupt_ch15outputF (False)DMA Done for channel 15 Interrupt port



Bus Master Ports

This model has the following bus master ports:

Bus Master Port: MREAD

Table 1: MREAD

NameAddress Width (bits)Description
MREAD32DMA Master Read of address space

Bus Master Port: MWRITE

Table 2: MWRITE

NameAddress Width (bits)Description
MWRITE32DMA Master Write of address space



Bus Slave Ports

This model has the following bus slave ports:

Bus Slave Port: bport1

Table 3: Bus Slave Port: bport1

NameSize (bytes)Must Be ConnectedDescription
bport10x2000F (False)

Table 4: Bus Slave Port: bport1 Registers:

NameOffsetWidth (bits)DescriptionR/Wis Volatile
ab_CR0x032Control Register, offset: 0x0
ab_ES0x432Error Status Register, offset: 0x4
ab_ERQ0xc32Enable Request Register, offset: 0xC
ab_EEI0x1432
ab_CS_EEI_ERC0x1832Clear/Set EEI, ERC
ab_DNE_SRT_ERR_INT0x1c32Clear/Set DNE, START, ERR, INT registers
ab_INT0x2432
ab_ERR0x2c32Error Register, offset: 0x2C
ab_HRS0x3432
ab_DCHPRI3_00x10032Channel n Priority Registers 3 to 0
ab_DCHPRI7_40x10432
ab_DCHPRI11_80x10832
ab_DCHPRI15_120x10c32
ab_DCHPRI19_160x11032
ab_DCHPRI23_200x11432
ab_DCHPRI27_240x11832
ab_DCHPRI31_280x11c32
ab_TCD0_SADDR0x100032TCD Source Address
ab_TCD0_SOFF_ATTR0x100432TCD Signed Source Address Offset
ab_TCD0_NBYTES0x100832TCD Signed Minor Loop Offset, Minor Loop Disabled
ab_TCD0_SLAST0x100c32
ab_TCD0_DADDR0x101032
ab_TCD0_DOFF_CITER0x101432
ab_TCD0_DLASTSGA0x101832
ab_TCD0_CSR_BITER0x101c32
ab_TCD1_SADDR0x102032TCD Source Address
ab_TCD1_SOFF_ATTR0x102432TCD Signed Source Address Offset
ab_TCD1_NBYTES0x102832TCD Signed Minor Loop Offset, Minor Loop Disabled
ab_TCD1_SLAST0x102c32
ab_TCD1_DADDR0x103032
ab_TCD1_DOFF_CITER0x103432
ab_TCD1_DLASTSGA0x103832
ab_TCD1_CSR_BITER0x103c32
ab_TCD2_SADDR0x104032TCD Source Address
ab_TCD2_SOFF_ATTR0x104432TCD Signed Source Address Offset
ab_TCD2_NBYTES0x104832TCD Signed Minor Loop Offset, Minor Loop Disabled
ab_TCD2_SLAST0x104c32
ab_TCD2_DADDR0x105032
ab_TCD2_DOFF_CITER0x105432
ab_TCD2_DLASTSGA0x105832
ab_TCD2_CSR_BITER0x105c32
ab_TCD3_SADDR0x106032TCD Source Address
ab_TCD3_SOFF_ATTR0x106432TCD Signed Source Address Offset
ab_TCD3_NBYTES0x106832TCD Signed Minor Loop Offset, Minor Loop Disabled
ab_TCD3_SLAST0x106c32
ab_TCD3_DADDR0x107032
ab_TCD3_DOFF_CITER0x107432
ab_TCD3_DLASTSGA0x107832
ab_TCD3_CSR_BITER0x107c32
ab_TCD4_SADDR0x108032TCD Source Address
ab_TCD4_SOFF_ATTR0x108432TCD Signed Source Address Offset
ab_TCD4_NBYTES0x108832TCD Signed Minor Loop Offset, Minor Loop Disabled
ab_TCD4_SLAST0x108c32
ab_TCD4_DADDR0x109032
ab_TCD4_DOFF_CITER0x109432
ab_TCD4_DLASTSGA0x109832
ab_TCD4_CSR_BITER0x109c32
ab_TCD5_SADDR0x10a032TCD Source Address
ab_TCD5_SOFF_ATTR0x10a432TCD Signed Source Address Offset
ab_TCD5_NBYTES0x10a832TCD Signed Minor Loop Offset, Minor Loop Disabled
ab_TCD5_SLAST0x10ac32
ab_TCD5_DADDR0x10b032
ab_TCD5_DOFF_CITER0x10b432
ab_TCD5_DLASTSGA0x10b832
ab_TCD5_CSR_BITER0x10bc32
ab_TCD6_SADDR0x10c032TCD Source Address
ab_TCD6_SOFF_ATTR0x10c432TCD Signed Source Address Offset
ab_TCD6_NBYTES0x10c832TCD Signed Minor Loop Offset, Minor Loop Disabled
ab_TCD6_SLAST0x10cc32
ab_TCD6_DADDR0x10d032
ab_TCD6_DOFF_CITER0x10d432
ab_TCD6_DLASTSGA0x10d832
ab_TCD6_CSR_BITER0x10dc32
ab_TCD7_SADDR0x10e032TCD Source Address
ab_TCD7_SOFF_ATTR0x10e432TCD Signed Source Address Offset
ab_TCD7_NBYTES0x10e832TCD Signed Minor Loop Offset, Minor Loop Disabled
ab_TCD7_SLAST0x10ec32
ab_TCD7_DADDR0x10f032
ab_TCD7_DOFF_CITER0x10f432
ab_TCD7_DLASTSGA0x10f832
ab_TCD7_CSR_BITER0x10fc32
ab_TCD8_SADDR0x110032TCD Source Address
ab_TCD8_SOFF_ATTR0x110432TCD Signed Source Address Offset
ab_TCD8_NBYTES0x110832TCD Signed Minor Loop Offset, Minor Loop Disabled
ab_TCD8_SLAST0x110c32
ab_TCD8_DADDR0x111032
ab_TCD8_DOFF_CITER0x111432
ab_TCD8_DLASTSGA0x111832
ab_TCD8_CSR_BITER0x111c32
ab_TCD9_SADDR0x112032TCD Source Address
ab_TCD9_SOFF_ATTR0x112432TCD Signed Source Address Offset
ab_TCD9_NBYTES0x112832TCD Signed Minor Loop Offset, Minor Loop Disabled
ab_TCD9_SLAST0x112c32
ab_TCD9_DADDR0x113032
ab_TCD9_DOFF_CITER0x113432
ab_TCD9_DLASTSGA0x113832
ab_TCD9_CSR_BITER0x113c32
ab_TCD10_SADDR0x114032TCD Source Address
ab_TCD10_SOFF_ATTR0x114432TCD Signed Source Address Offset
ab_TCD10_NBYTES0x114832TCD Signed Minor Loop Offset, Minor Loop Disabled
ab_TCD10_SLAST0x114c32
ab_TCD10_DADDR0x115032
ab_TCD10_DOFF_CITER0x115432
ab_TCD10_DLASTSGA0x115832
ab_TCD10_CSR_BITER0x115c32
ab_TCD11_SADDR0x116032TCD Source Address
ab_TCD11_SOFF_ATTR0x116432TCD Signed Source Address Offset
ab_TCD11_NBYTES0x116832TCD Signed Minor Loop Offset, Minor Loop Disabled
ab_TCD11_SLAST0x116c32
ab_TCD11_DADDR0x117032
ab_TCD11_DOFF_CITER0x117432
ab_TCD11_DLASTSGA0x117832
ab_TCD11_CSR_BITER0x117c32
ab_TCD12_SADDR0x118032TCD Source Address
ab_TCD12_SOFF_ATTR0x118432TCD Signed Source Address Offset
ab_TCD12_NBYTES0x118832TCD Signed Minor Loop Offset, Minor Loop Disabled
ab_TCD12_SLAST0x118c32
ab_TCD12_DADDR0x119032
ab_TCD12_DOFF_CITER0x119432
ab_TCD12_DLASTSGA0x119832
ab_TCD12_CSR_BITER0x119c32
ab_TCD13_SADDR0x11a032TCD Source Address
ab_TCD13_SOFF_ATTR0x11a432TCD Signed Source Address Offset
ab_TCD13_NBYTES0x11a832TCD Signed Minor Loop Offset, Minor Loop Disabled
ab_TCD13_SLAST0x11ac32
ab_TCD13_DADDR0x11b032
ab_TCD13_DOFF_CITER0x11b432
ab_TCD13_DLASTSGA0x11b832
ab_TCD13_CSR_BITER0x11bc32
ab_TCD14_SADDR0x11c032TCD Source Address
ab_TCD14_SOFF_ATTR0x11c432TCD Signed Source Address Offset
ab_TCD14_NBYTES0x11c832TCD Signed Minor Loop Offset, Minor Loop Disabled
ab_TCD14_SLAST0x11cc32
ab_TCD14_DADDR0x11d032
ab_TCD14_DOFF_CITER0x11d432
ab_TCD14_DLASTSGA0x11d832
ab_TCD14_CSR_BITER0x11dc32
ab_TCD15_SADDR0x11e032TCD Source Address
ab_TCD15_SOFF_ATTR0x11e432TCD Signed Source Address Offset
ab_TCD15_NBYTES0x11e832TCD Signed Minor Loop Offset, Minor Loop Disabled
ab_TCD15_SLAST0x11ec32
ab_TCD15_DADDR0x11f032
ab_TCD15_DOFF_CITER0x11f432
ab_TCD15_DLASTSGA0x11f832
ab_TCD15_CSR_BITER0x11fc32
ab_TCD16_SADDR0x120032TCD Source Address
ab_TCD16_SOFF_ATTR0x120432TCD Signed Source Address Offset
ab_TCD16_NBYTES0x120832TCD Signed Minor Loop Offset, Minor Loop Disabled
ab_TCD16_SLAST0x120c32
ab_TCD16_DADDR0x121032
ab_TCD16_DOFF_CITER0x121432
ab_TCD16_DLASTSGA0x121832
ab_TCD16_CSR_BITER0x121c32
ab_TCD17_SADDR0x122032TCD Source Address
ab_TCD17_SOFF_ATTR0x122432TCD Signed Source Address Offset
ab_TCD17_NBYTES0x122832TCD Signed Minor Loop Offset, Minor Loop Disabled
ab_TCD17_SLAST0x122c32
ab_TCD17_DADDR0x123032
ab_TCD17_DOFF_CITER0x123432
ab_TCD17_DLASTSGA0x123832
ab_TCD17_CSR_BITER0x123c32
ab_TCD18_SADDR0x124032TCD Source Address
ab_TCD18_SOFF_ATTR0x124432TCD Signed Source Address Offset
ab_TCD18_NBYTES0x124832TCD Signed Minor Loop Offset, Minor Loop Disabled
ab_TCD18_SLAST0x124c32
ab_TCD18_DADDR0x125032
ab_TCD18_DOFF_CITER0x125432
ab_TCD18_DLASTSGA0x125832
ab_TCD18_CSR_BITER0x125c32
ab_TCD19_SADDR0x126032TCD Source Address
ab_TCD19_SOFF_ATTR0x126432TCD Signed Source Address Offset
ab_TCD19_NBYTES0x126832TCD Signed Minor Loop Offset, Minor Loop Disabled
ab_TCD19_SLAST0x126c32
ab_TCD19_DADDR0x127032
ab_TCD19_DOFF_CITER0x127432
ab_TCD19_DLASTSGA0x127832
ab_TCD19_CSR_BITER0x127c32
ab_TCD20_SADDR0x128032TCD Source Address
ab_TCD20_SOFF_ATTR0x128432TCD Signed Source Address Offset
ab_TCD20_NBYTES0x128832TCD Signed Minor Loop Offset, Minor Loop Disabled
ab_TCD20_SLAST0x128c32
ab_TCD20_DADDR0x129032
ab_TCD20_DOFF_CITER0x129432
ab_TCD20_DLASTSGA0x129832
ab_TCD20_CSR_BITER0x129c32
ab_TCD21_SADDR0x12a032TCD Source Address
ab_TCD21_SOFF_ATTR0x12a432TCD Signed Source Address Offset
ab_TCD21_NBYTES0x12a832TCD Signed Minor Loop Offset, Minor Loop Disabled
ab_TCD21_SLAST0x12ac32
ab_TCD21_DADDR0x12b032
ab_TCD21_DOFF_CITER0x12b432
ab_TCD21_DLASTSGA0x12b832
ab_TCD21_CSR_BITER0x12bc32
ab_TCD22_SADDR0x12c032TCD Source Address
ab_TCD22_SOFF_ATTR0x12c432TCD Signed Source Address Offset
ab_TCD22_NBYTES0x12c832TCD Signed Minor Loop Offset, Minor Loop Disabled
ab_TCD22_SLAST0x12cc32
ab_TCD22_DADDR0x12d032
ab_TCD22_DOFF_CITER0x12d432
ab_TCD22_DLASTSGA0x12d832
ab_TCD22_CSR_BITER0x12dc32
ab_TCD23_SADDR0x12e032TCD Source Address
ab_TCD23_SOFF_ATTR0x12e432TCD Signed Source Address Offset
ab_TCD23_NBYTES0x12e832TCD Signed Minor Loop Offset, Minor Loop Disabled
ab_TCD23_SLAST0x12ec32
ab_TCD23_DADDR0x12f032
ab_TCD23_DOFF_CITER0x12f432
ab_TCD23_DLASTSGA0x12f832
ab_TCD23_CSR_BITER0x12fc32
ab_TCD24_SADDR0x130032TCD Source Address
ab_TCD24_SOFF_ATTR0x130432TCD Signed Source Address Offset
ab_TCD24_NBYTES0x130832TCD Signed Minor Loop Offset, Minor Loop Disabled
ab_TCD24_SLAST0x130c32
ab_TCD24_DADDR0x131032
ab_TCD24_DOFF_CITER0x131432
ab_TCD24_DLASTSGA0x131832
ab_TCD24_CSR_BITER0x131c32
ab_TCD25_SADDR0x132032TCD Source Address
ab_TCD25_SOFF_ATTR0x132432TCD Signed Source Address Offset
ab_TCD25_NBYTES0x132832TCD Signed Minor Loop Offset, Minor Loop Disabled
ab_TCD25_SLAST0x132c32
ab_TCD25_DADDR0x133032
ab_TCD25_DOFF_CITER0x133432
ab_TCD25_DLASTSGA0x133832
ab_TCD25_CSR_BITER0x133c32
ab_TCD26_SADDR0x134032TCD Source Address
ab_TCD26_SOFF_ATTR0x134432TCD Signed Source Address Offset
ab_TCD26_NBYTES0x134832TCD Signed Minor Loop Offset, Minor Loop Disabled
ab_TCD26_SLAST0x134c32
ab_TCD26_DADDR0x135032
ab_TCD26_DOFF_CITER0x135432
ab_TCD26_DLASTSGA0x135832
ab_TCD26_CSR_BITER0x135c32
ab_TCD27_SADDR0x136032TCD Source Address
ab_TCD27_SOFF_ATTR0x136432TCD Signed Source Address Offset
ab_TCD27_NBYTES0x136832TCD Signed Minor Loop Offset, Minor Loop Disabled
ab_TCD27_SLAST0x136c32
ab_TCD27_DADDR0x137032
ab_TCD27_DOFF_CITER0x137432
ab_TCD27_DLASTSGA0x137832
ab_TCD27_CSR_BITER0x137c32
ab_TCD28_SADDR0x138032TCD Source Address
ab_TCD28_SOFF_ATTR0x138432TCD Signed Source Address Offset
ab_TCD28_NBYTES0x138832TCD Signed Minor Loop Offset, Minor Loop Disabled
ab_TCD28_SLAST0x138c32
ab_TCD28_DADDR0x139032
ab_TCD28_DOFF_CITER0x139432
ab_TCD28_DLASTSGA0x139832
ab_TCD28_CSR_BITER0x139c32
ab_TCD29_SADDR0x13a032TCD Source Address
ab_TCD29_SOFF_ATTR0x13a432TCD Signed Source Address Offset
ab_TCD29_NBYTES0x13a832TCD Signed Minor Loop Offset, Minor Loop Disabled
ab_TCD29_SLAST0x13ac32
ab_TCD29_DADDR0x13b032
ab_TCD29_DOFF_CITER0x13b432
ab_TCD29_DLASTSGA0x13b832
ab_TCD29_CSR_BITER0x13bc32
ab_TCD30_SADDR0x13c032TCD Source Address
ab_TCD30_SOFF_ATTR0x13c432TCD Signed Source Address Offset
ab_TCD30_NBYTES0x13c832TCD Signed Minor Loop Offset, Minor Loop Disabled
ab_TCD30_SLAST0x13cc32
ab_TCD30_DADDR0x13d032
ab_TCD30_DOFF_CITER0x13d432
ab_TCD30_DLASTSGA0x13d832
ab_TCD30_CSR_BITER0x13dc32
ab_TCD31_SADDR0x13e032TCD Source Address
ab_TCD31_SOFF_ATTR0x13e432TCD Signed Source Address Offset
ab_TCD31_NBYTES0x13e832TCD Signed Minor Loop Offset, Minor Loop Disabled
ab_TCD31_SLAST0x13ec32
ab_TCD31_DADDR0x13f032
ab_TCD31_DOFF_CITER0x13f432
ab_TCD31_DLASTSGA0x13f832
ab_TCD31_CSR_BITER0x13fc32



Platforms that use this peripheral component

Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.

Table 5: Publicly available platforms using peripheral 'KinetisDMA'

Platform NameVendor
FreescaleKinetis60freescale.ovpworld.org
FreescaleKinetis64freescale.ovpworld.org



FreescalePeripherals
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