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FreescaleKinetisDMAC



OVP Peripheral Model: FreescaleKinetisDMAC



Model Specific Information

This page provides introductory usage information for an Imperas OVP peripheral behavioral model. The page is split into sections providing specific information for this peripheral, including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.

Description

Freescale Kinetis Direct Memory Access Controller

Limitations

Only models control register read/write - control register CX and ECX bits are modeled as RAZ/WI

Licensing

Open Source Apache 2.0

Reference

Freescale Kinetis Peripheral User Guide

Location

The KinetisDMAC peripheral model is located in an Imperas/OVP installation at the VLNV: freescale.ovpworld.org / peripheral / KinetisDMAC / 1.0.



Net Ports

This model has the following net ports:

Table : Net Ports

NameTypeMust Be ConnectedDescription
ResetinputF (False)



Bus Slave Ports

This model has the following bus slave ports:

Bus Slave Port: bport1

Table 1: Bus Slave Port: bport1

NameSize (bytes)Must Be ConnectedDescription
bport10x1000F (False)

Table 2: Bus Slave Port: bport1 Registers:

NameOffsetWidth (bits)DescriptionR/Wis Volatile
ab_cr0x032DMAC Control Register



FreescalePeripherals
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