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FreescaleKinetisENET



OVP Peripheral Model: FreescaleKinetisENET



Model Specific Information

This page provides introductory usage information for an Imperas OVP peripheral behavioral model. The page is split into sections providing specific information for this peripheral, including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.

Description

Model of the ENET peripheral used on the Freescale Kinetis platform

Limitations

Provides the base behaviour for the OVP Freescale Kinetis platforms

Reference

www.freescale.com/Kinetis

Licensing

Open Source Apache 2.0

Location

The KinetisENET peripheral model is located in an Imperas/OVP installation at the VLNV: freescale.ovpworld.org / peripheral / KinetisENET / 1.0.



Net Ports

This model has the following net ports:

Table : Net Ports

NameTypeMust Be ConnectedDescription
ResetinputF (False)



Bus Slave Ports

This model has the following bus slave ports:

Bus Slave Port: bport1

Table 1: Bus Slave Port: bport1

NameSize (bytes)Must Be ConnectedDescription
bport10x1000F (False)

Table 2: Bus Slave Port: bport1 Registers:

NameOffsetWidth (bits)DescriptionR/Wis Volatile
ab_EIR0x432Interrupt Event Register, offset: 0x4
ab_EIMR0x832Interrupt Mask Register, offset: 0x8
ab_RDAR0x1032Receive Descriptor Active Register, offset: 0x10
ab_TDAR0x1432Transmit Descriptor Active Register, offset: 0x14
ab_ECR0x2432Ethernet Control Register, offset: 0x24
ab_MMFR0x4032MII Management Frame Register, offset: 0x40
ab_MSCR0x4432MII Speed Control Register, offset: 0x44
ab_MIBC0x6432MIB Control Register, offset: 0x64
ab_RCR0x8432Receive Control Register, offset: 0x84
ab_TCR0xc432Transmit Control Register, offset: 0xC4
ab_PALR0xe432Physical Address Lower Register, offset: 0xE4
ab_PAUR0xe832Physical Address Upper Register, offset: 0xE8
ab_OPD0xec32Opcode/Pause Duration Register, offset: 0xEC
ab_IAUR0x11832Descriptor Individual Upper Address Register, offset: 0x118
ab_IALR0x11c32Descriptor Individual Lower Address Register, offset: 0x11C
ab_GAUR0x12032Descriptor Group Upper Address Register, offset: 0x120
ab_GALR0x12432Descriptor Group Lower Address Register, offset: 0x124
ab_TFWR0x14432Transmit FIFO Watermark Register, offset: 0x144
ab_RDSR0x18032Receive Descriptor Ring Start Register, offset: 0x180
ab_TDSR0x18432Transmit Buffer Descriptor Ring Start Register, offset: 0x184
ab_MRBR0x18832Maximum Receive Buffer Size Register, offset: 0x188
ab_RSFL0x19032Receive FIFO Section Full Threshold, offset: 0x190
ab_RSEM0x19432Receive FIFO Section Empty Threshold, offset: 0x194
ab_RAEM0x19832Receive FIFO Almost Empty Threshold, offset: 0x198
ab_RAFL0x19c32Receive FIFO Almost Full Threshold, offset: 0x19C
ab_TSEM0x1a032Transmit FIFO Section Empty Threshold, offset: 0x1A0
ab_TAEM0x1a432Transmit FIFO Almost Empty Threshold, offset: 0x1A4
ab_TAFL0x1a832Transmit FIFO Almost Full Threshold, offset: 0x1A8
ab_TIPG0x1ac32Transmit Inter-Packet Gap, offset: 0x1AC
ab_FTRL0x1b032Frame Truncation Length, offset: 0x1B0
ab_TACC0x1c032Transmit Accelerator Function Configuration, offset: 0x1C0
ab_RACC0x1c432Receive Accelerator Function Configuration, offset: 0x1C4
ab_RMON_T_DROP0x20032Count of frames not counted correctly (RMON_T_DROP). NOTE: Counter not implemented (read 0 always) as not applicable., offset: 0x200
ab_RMON_T_PACKETS0x20432RMON Tx packet count (RMON_T_PACKETS), offset: 0x204
ab_RMON_T_BC_PKT0x20832RMON Tx Broadcast Packets (RMON_T_BC_PKT), offset: 0x208
ab_RMON_T_MC_PKT0x20c32RMON Tx Multicast Packets (RMON_T_MC_PKT), offset: 0x20C
ab_RMON_T_CRC_ALIGN0x21032RMON Tx Packets w CRC/Align error (RMON_T_CRC_ALIGN), offset: 0x210
ab_RMON_T_UNDERSIZE0x21432RMON Tx Packets < 64 bytes, good CRC (RMON_T_UNDERSIZE), offset: 0x214
ab_RMON_T_OVERSIZE0x21832RMON Tx Packets > MAX_FL bytes, good CRC (RMON_T_OVERSIZE), offset: 0x218
ab_RMON_T_FRAG0x21c32RMON Tx Packets < 64 bytes, bad CRC (RMON_T_FRAG), offset: 0x21C
ab_RMON_T_JAB0x22032RMON Tx Packets > MAX_FL bytes, bad CRC (RMON_T_JAB), offset: 0x220
ab_RMON_T_COL0x22432RMON Tx collision count (RMON_T_COL), offset: 0x224
ab_RMON_T_P640x22832RMON Tx 64 byte packets (RMON_T_P64), offset: 0x228
ab_RMON_T_P65TO1270x22c32RMON Tx 65 to 127 byte packets (RMON_T_P65TO127), offset: 0x22C
ab_RMON_T_P128TO2550x23032RMON Tx 128 to 255 byte packets (RMON_T_P128TO255), offset: 0x230
ab_RMON_T_P256TO5110x23432RMON Tx 256 to 511 byte packets (RMON_T_P256TO511), offset: 0x234
ab_RMON_T_P512TO10230x23832RMON Tx 512 to 1023 byte packets (RMON_T_P512TO1023), offset: 0x238
ab_RMON_T_P1024TO20470x23c32RMON Tx 1024 to 2047 byte packets (RMON_T_P1024TO2047), offset: 0x23C
ab_RMON_T_P_GTE20480x24032RMON Tx packets w > 2048 bytes (RMON_T_P_GTE2048), offset: 0x240
ab_RMON_T_OCTETS0x24432RMON Tx Octets (RMON_T_OCTETS), offset: 0x244
ab_IEEE_T_DROP0x24832Count of frames not counted correctly (IEEE_T_DROP). NOTE: Counter not implemented (read 0 always) as not applicable., offset: 0x248
ab_IEEE_T_FRAME_OK0x24c32Frames Transmitted OK (IEEE_T_FRAME_OK), offset: 0x24C
ab_IEEE_T_1COL0x25032Frames Transmitted with Single Collision (IEEE_T_1COL), offset: 0x250
ab_IEEE_T_MCOL0x25432Frames Transmitted with Multiple Collisions (IEEE_T_MCOL), offset: 0x254
ab_IEEE_T_DEF0x25832Frames Transmitted after Deferral Delay (IEEE_T_DEF), offset: 0x258
ab_IEEE_T_LCOL0x25c32Frames Transmitted with Late Collision (IEEE_T_LCOL), offset: 0x25C
ab_IEEE_T_EXCOL0x26032Frames Transmitted with Excessive Collisions (IEEE_T_EXCOL), offset: 0x260
ab_IEEE_T_MACERR0x26432Frames Transmitted with Tx FIFO Underrun (IEEE_T_MACERR), offset: 0x264
ab_IEEE_T_CSERR0x26832Frames Transmitted with Carrier Sense Error (IEEE_T_CSERR), offset: 0x268
ab_IEEE_T_SQE0x26c32Frames Transmitted with SQE Error (IEEE_T_SQE). NOTE: Counter not implemented (read 0 always) as no SQE information is available., offset: 0x26C
ab_IEEE_T_FDXFC0x27032Flow Control Pause frames transmitted (IEEE_T_FDXFC), offset: 0x270
ab_IEEE_T_OCTETS_OK0x27432Octet count for Frames Transmitted w/o Error (IEEE_T_OCTETS_OK). NOTE: Counts total octets (includes header and FCS fields)., offset: 0x274
ab_RMON_R_PACKETS0x28432RMON Rx packet count (RMON_R_PACKETS), offset: 0x284
ab_RMON_R_BC_PKT0x28832RMON Rx Broadcast Packets (RMON_R_BC_PKT), offset: 0x288
ab_RMON_R_MC_PKT0x28c32RMON Rx Multicast Packets (RMON_R_MC_PKT), offset: 0x28C
ab_RMON_R_CRC_ALIGN0x29032RMON Rx Packets w CRC/Align error (RMON_R_CRC_ALIGN), offset: 0x290
ab_RMON_R_UNDERSIZE0x29432RMON Rx Packets < 64 bytes, good CRC (RMON_R_UNDERSIZE), offset: 0x294
ab_RMON_R_OVERSIZE0x29832RMON Rx Packets > MAX_FL bytes, good CRC (RMON_R_OVERSIZE), offset: 0x298
ab_RMON_R_FRAG0x29c32RMON Rx Packets < 64 bytes, bad CRC (RMON_R_FRAG), offset: 0x29C
ab_RMON_R_JAB0x2a032RMON Rx Packets > MAX_FL bytes, bad CRC (RMON_R_JAB), offset: 0x2A0
ab_RMON_R_RESVD_00x2a432Reserved (RMON_R_RESVD_0), offset: 0x2A4
ab_RMON_R_P640x2a832RMON Rx 64 byte packets (RMON_R_P64), offset: 0x2A8
ab_RMON_R_P65TO1270x2ac32RMON Rx 65 to 127 byte packets (RMON_R_P65TO127), offset: 0x2AC
ab_RMON_R_P128TO2550x2b032RMON Rx 128 to 255 byte packets (RMON_R_P128TO255), offset: 0x2B0
ab_RMON_R_P256TO5110x2b432RMON Rx 256 to 511 byte packets (RMON_R_P256TO511), offset: 0x2B4
ab_RMON_R_P512TO10230x2b832RMON Rx 512 to 1023 byte packets (RMON_R_P512TO1023), offset: 0x2B8
ab_RMON_R_P1024TO20470x2bc32RMON Rx 1024 to 2047 byte packets (RMON_R_P1024TO2047), offset: 0x2BC
ab_RMON_R_P_GTE20480x2c032RMON Rx packets w > 2048 bytes (RMON_R_P_GTE2048), offset: 0x2C0
ab_RMON_R_OCTETS0x2c432RMON Rx Octets (RMON_R_OCTETS), offset: 0x2C4
ab_RMON_R_DROP0x2c832Count of frames not counted correctly (IEEE_R_DROP). NOTE: Counter increments if a frame with valid/missing SFD character is detected and has been dropped. None of the other counters increments if this counter increments., offset: 0x2C8
ab_RMON_R_FRAME_OK0x2cc32Frames Received OK (IEEE_R_FRAME_OK), offset: 0x2CC
ab_IEEE_R_CRC0x2d032Frames Received with CRC Error (IEEE_R_CRC), offset: 0x2D0
ab_IEEE_R_ALIGN0x2d432Frames Received with Alignment Error (IEEE_R_ALIGN), offset: 0x2D4
ab_IEEE_R_MACERR0x2d832Receive Fifo Overflow count (IEEE_R_MACERR), offset: 0x2D8
ab_IEEE_R_FDXFC0x2dc32Flow Control Pause frames received (IEEE_R_FDXFC), offset: 0x2DC
ab_IEEE_R_OCTETS_OK0x2e032Octet count for Frames Rcvd w/o Error (IEEE_R_OCTETS_OK). Counts total octets (includes header and FCS fields)., offset: 0x2E0
ab_ATCR0x40032Timer Control Register, offset: 0x400
ab_ATVR0x40432Timer Value Register, offset: 0x404
ab_ATOFF0x40832Timer Offset Register, offset: 0x408
ab_ATPER0x40c32Timer Period Register, offset: 0x40C
ab_ATCOR0x41032Timer Correction Register, offset: 0x410
ab_ATINC0x41432Time-Stamping Clock Period Register, offset: 0x414
ab_ATSTMP0x41832Timestamp of Last Transmitted Frame, offset: 0x418
ab_TGSR0x60432Timer Global Status Register, offset: 0x604
ab_TCSR00x60832Timer Control Status Register, array offset: 0x608, array step: 0x8
ab_TCCR00x60c32Timer Compare Capture Register, array offset: 0x60C, array step: 0x8
ab_TCSR10x61032Timer Control Status Register, array offset: 0x610, array step: 0x8
ab_TCCR10x61432Timer Compare Capture Register, array offset: 0x614, array step: 0x8
ab_TCSR20x61832Timer Control Status Register, array offset: 0x618, array step: 0x8
ab_TCCR20x61c32Timer Compare Capture Register, array offset: 0x61c, array step: 0x8
ab_TCSR30x62032Timer Control Status Register, array offset: 0x620, array step: 0x8
ab_TCCR30x62432Timer Compare Capture Register, array offset: 0x624, array step: 0x8



Platforms that use this peripheral component

Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.

Table 3: Publicly available platforms using peripheral 'KinetisENET'

Platform NameVendor
FreescaleKinetis60freescale.ovpworld.org
FreescaleKinetis64freescale.ovpworld.org



FreescalePeripherals
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