Name | Type | Must Be Connected | Description |
---|---|---|---|
Reset | input | F (False) |
Table : Net Ports
Name | Type | Must Be Connected | Description |
---|---|---|---|
Reset | input | F (False) |
Table 1: Bus Slave Port: bport1
Name | Size (bytes) | Must Be Connected | Description |
---|---|---|---|
bport1 | 0x1000 | F (False) |
Table 2: Bus Slave Port: bport1 Registers:
Name | Offset | Width (bits) | Description | R/W | is Volatile |
---|---|---|---|---|---|
ab_PFAPR | 0x0 | 32 | Flash Access Protection Register, offset: 0x0 | ||
ab_PFB01CR | 0x4 | 32 | Flash Bank 0-1 Control Register, offset: 0x4 | ||
ab_PFB23CR | 0x8 | 32 | Flash Bank 2-3 Control Register, offset: 0x8 | ||
ab_TAGVDW0S0 | 0x100 | 32 | Cache Tag Storage, array offset: 0x100, array step: index*0x10, index2*0x4 | ||
ab_TAGVDW0S1 | 0x104 | 32 | Cache Tag Storage, array offset: 0x100, array step: index*0x10, index2*0x4 | ||
ab_TAGVDW0S2 | 0x108 | 32 | Cache Tag Storage, array offset: 0x100, array step: index*0x10, index2*0x4 | ||
ab_TAGVDW0S3 | 0x10c | 32 | Cache Tag Storage, array offset: 0x100, array step: index*0x10, index2*0x4 | ||
ab_TAGVDW1S0 | 0x110 | 32 | Cache Tag Storage, array offset: 0x100, array step: index*0x10, index2*0x4 | ||
ab_TAGVDW1S1 | 0x114 | 32 | Cache Tag Storage, array offset: 0x100, array step: index*0x10, index2*0x4 | ||
ab_TAGVDW1S2 | 0x118 | 32 | Cache Tag Storage, array offset: 0x100, array step: index*0x10, index2*0x4 | ||
ab_TAGVDW1S3 | 0x11c | 32 | Cache Tag Storage, array offset: 0x100, array step: index*0x10, index2*0x4 | ||
ab_TAGVDW2S0 | 0x120 | 32 | Cache Tag Storage, array offset: 0x100, array step: index*0x10, index2*0x4 | ||
ab_TAGVDW2S1 | 0x124 | 32 | Cache Tag Storage, array offset: 0x100, array step: index*0x10, index2*0x4 | ||
ab_TAGVDW2S2 | 0x128 | 32 | Cache Tag Storage, array offset: 0x100, array step: index*0x10, index2*0x4 | ||
ab_TAGVDW2S3 | 0x12c | 32 | Cache Tag Storage, array offset: 0x100, array step: index*0x10, index2*0x4 | ||
ab_TAGVDW3S0 | 0x130 | 32 | Cache Tag Storage, array offset: 0x100, array step: index*0x10, index2*0x4 | ||
ab_TAGVDW3S1 | 0x134 | 32 | Cache Tag Storage, array offset: 0x100, array step: index*0x10, index2*0x4 | ||
ab_TAGVDW3S2 | 0x138 | 32 | Cache Tag Storage, array offset: 0x100, array step: index*0x10, index2*0x4 | ||
ab_TAGVDW3S3 | 0x13c | 32 | Cache Tag Storage, array offset: 0x100, array step: index*0x10, index2*0x4 | ||
ab_DATAW0S0UM | 0x200 | 32 | Cache Data Storage (uppermost word), array offset: 0x200, array step: index*0x40, index2*0x10 | ||
ab_DATAW0S0MU | 0x204 | 32 | Cache Data Storage (mid-upper word), array offset: 0x204, array step: index*0x40, index2*0x10 | ||
ab_DATAW0S0ML | 0x208 | 32 | Cache Data Storage (mid-lower word), array offset: 0x208, array step: index*0x40, index2*0x10 | ||
ab_DATAW0S0LM | 0x20c | 32 | Cache Data Storage (lowermost word), array offset: 0x20C, array step: index*0x40, index2*0x10 | ||
ab_DATAW0S1UM | 0x210 | 32 | Cache Data Storage (uppermost word), array offset: 0x200, array step: index*0x40, index2*0x10 | ||
ab_DATAW0S1MU | 0x214 | 32 | Cache Data Storage (mid-upper word), array offset: 0x204, array step: index*0x40, index2*0x10 | ||
ab_DATAW0S1ML | 0x218 | 32 | Cache Data Storage (mid-lower word), array offset: 0x208, array step: index*0x40, index2*0x10 | ||
ab_DATAW0S1LM | 0x21c | 32 | Cache Data Storage (lowermost word), array offset: 0x20C, array step: index*0x40, index2*0x10 | ||
ab_DATAW0S2UM | 0x220 | 32 | Cache Data Storage (uppermost word), array offset: 0x200, array step: index*0x40, index2*0x10 | ||
ab_DATAW0S2MU | 0x224 | 32 | Cache Data Storage (mid-upper word), array offset: 0x204, array step: index*0x40, index2*0x10 | ||
ab_DATAW0S2ML | 0x228 | 32 | Cache Data Storage (mid-lower word), array offset: 0x208, array step: index*0x40, index2*0x10 | ||
ab_DATAW0S2LM | 0x22c | 32 | Cache Data Storage (lowermost word), array offset: 0x20C, array step: index*0x40, index2*0x10 | ||
ab_DATAW0S3UM | 0x230 | 32 | Cache Data Storage (uppermost word), array offset: 0x200, array step: index*0x40, index2*0x10 | ||
ab_DATAW0S3MU | 0x234 | 32 | Cache Data Storage (mid-upper word), array offset: 0x204, array step: index*0x40, index2*0x10 | ||
ab_DATAW0S3ML | 0x238 | 32 | Cache Data Storage (mid-lower word), array offset: 0x208, array step: index*0x40, index2*0x10 | ||
ab_DATAW0S3LM | 0x23c | 32 | Cache Data Storage (lowermost word), array offset: 0x20C, array step: index*0x40, index2*0x10 | ||
ab_DATAW1S0UM | 0x240 | 32 | Cache Data Storage (uppermost word), array offset: 0x200, array step: index*0x40, index2*0x10 | ||
ab_DATAW1S0MU | 0x244 | 32 | Cache Data Storage (mid-upper word), array offset: 0x204, array step: index*0x40, index2*0x10 | ||
ab_DATAW1S0ML | 0x248 | 32 | Cache Data Storage (mid-lower word), array offset: 0x208, array step: index*0x40, index2*0x10 | ||
ab_DATAW1S0LM | 0x24c | 32 | Cache Data Storage (lowermost word), array offset: 0x20C, array step: index*0x40, index2*0x10 | ||
ab_DATAW1S1UM | 0x250 | 32 | Cache Data Storage (uppermost word), array offset: 0x200, array step: index*0x40, index2*0x10 | ||
ab_DATAW1S1MU | 0x254 | 32 | Cache Data Storage (mid-upper word), array offset: 0x204, array step: index*0x40, index2*0x10 | ||
ab_DATAW1S1ML | 0x258 | 32 | Cache Data Storage (mid-lower word), array offset: 0x208, array step: index*0x40, index2*0x10 | ||
ab_DATAW1S1LM | 0x25c | 32 | Cache Data Storage (lowermost word), array offset: 0x20C, array step: index*0x40, index2*0x10 | ||
ab_DATAW1S2UM | 0x260 | 32 | Cache Data Storage (uppermost word), array offset: 0x200, array step: index*0x40, index2*0x10 | ||
ab_DATAW1S2MU | 0x264 | 32 | Cache Data Storage (mid-upper word), array offset: 0x204, array step: index*0x40, index2*0x10 | ||
ab_DATAW1S2ML | 0x268 | 32 | Cache Data Storage (mid-lower word), array offset: 0x208, array step: index*0x40, index2*0x10 | ||
ab_DATAW1S2LM | 0x26c | 32 | Cache Data Storage (lowermost word), array offset: 0x20C, array step: index*0x40, index2*0x10 | ||
ab_DATAW1S3UM | 0x270 | 32 | Cache Data Storage (uppermost word), array offset: 0x200, array step: index*0x40, index2*0x10 | ||
ab_DATAW1S3MU | 0x274 | 32 | Cache Data Storage (mid-upper word), array offset: 0x204, array step: index*0x40, index2*0x10 | ||
ab_DATAW1S3ML | 0x278 | 32 | Cache Data Storage (mid-lower word), array offset: 0x208, array step: index*0x40, index2*0x10 | ||
ab_DATAW1S3LM | 0x27c | 32 | Cache Data Storage (lowermost word), array offset: 0x20C, array step: index*0x40, index2*0x10 | ||
ab_DATAW2S0UM | 0x280 | 32 | Cache Data Storage (uppermost word), array offset: 0x200, array step: index*0x40, index2*0x10 | ||
ab_DATAW2S0MU | 0x284 | 32 | Cache Data Storage (mid-upper word), array offset: 0x204, array step: index*0x40, index2*0x10 | ||
ab_DATAW2S0ML | 0x288 | 32 | Cache Data Storage (mid-lower word), array offset: 0x208, array step: index*0x40, index2*0x10 | ||
ab_DATAW2S0LM | 0x28c | 32 | Cache Data Storage (lowermost word), array offset: 0x20C, array step: index*0x40, index2*0x10 | ||
ab_DATAW2S1UM | 0x290 | 32 | Cache Data Storage (uppermost word), array offset: 0x200, array step: index*0x40, index2*0x10 | ||
ab_DATAW2S1MU | 0x294 | 32 | Cache Data Storage (mid-upper word), array offset: 0x204, array step: index*0x40, index2*0x10 | ||
ab_DATAW2S1ML | 0x298 | 32 | Cache Data Storage (mid-lower word), array offset: 0x208, array step: index*0x40, index2*0x10 | ||
ab_DATAW2S1LM | 0x29c | 32 | Cache Data Storage (lowermost word), array offset: 0x20C, array step: index*0x40, index2*0x10 | ||
ab_DATAW2S2UM | 0x2a0 | 32 | Cache Data Storage (uppermost word), array offset: 0x200, array step: index*0x40, index2*0x10 | ||
ab_DATAW2S2MU | 0x2a4 | 32 | Cache Data Storage (mid-upper word), array offset: 0x204, array step: index*0x40, index2*0x10 | ||
ab_DATAW2S2ML | 0x2a8 | 32 | Cache Data Storage (mid-lower word), array offset: 0x208, array step: index*0x40, index2*0x10 | ||
ab_DATAW2S2LM | 0x2ac | 32 | Cache Data Storage (lowermost word), array offset: 0x20C, array step: index*0x40, index2*0x10 | ||
ab_DATAW2S3UM | 0x2b0 | 32 | Cache Data Storage (uppermost word), array offset: 0x200, array step: index*0x40, index2*0x10 | ||
ab_DATAW2S3MU | 0x2b4 | 32 | Cache Data Storage (mid-upper word), array offset: 0x204, array step: index*0x40, index2*0x10 | ||
ab_DATAW2S3ML | 0x2b8 | 32 | Cache Data Storage (mid-lower word), array offset: 0x208, array step: index*0x40, index2*0x10 | ||
ab_DATAW2S3LM | 0x2bc | 32 | Cache Data Storage (lowermost word), array offset: 0x20C, array step: index*0x40, index2*0x10 | ||
ab_DATAW3S0UM | 0x2c0 | 32 | Cache Data Storage (uppermost word), array offset: 0x200, array step: index*0x40, index2*0x10 | ||
ab_DATAW3S0MU | 0x2c4 | 32 | Cache Data Storage (mid-upper word), array offset: 0x204, array step: index*0x40, index2*0x10 | ||
ab_DATAW3S0ML | 0x2c8 | 32 | Cache Data Storage (mid-lower word), array offset: 0x208, array step: index*0x40, index2*0x10 | ||
ab_DATAW3S0LM | 0x2cc | 32 | Cache Data Storage (lowermost word), array offset: 0x20C, array step: index*0x40, index2*0x10 | ||
ab_DATAW3S1UM | 0x2d0 | 32 | Cache Data Storage (uppermost word), array offset: 0x200, array step: index*0x40, index2*0x10 | ||
ab_DATAW3S1MU | 0x2d4 | 32 | Cache Data Storage (mid-upper word), array offset: 0x204, array step: index*0x40, index2*0x10 | ||
ab_DATAW3S1ML | 0x2d8 | 32 | Cache Data Storage (mid-lower word), array offset: 0x208, array step: index*0x40, index2*0x10 | ||
ab_DATAW3S1LM | 0x2dc | 32 | Cache Data Storage (lowermost word), array offset: 0x20C, array step: index*0x40, index2*0x10 | ||
ab_DATAW3S2UM | 0x2e0 | 32 | Cache Data Storage (uppermost word), array offset: 0x200, array step: index*0x40, index2*0x10 | ||
ab_DATAW3S2MU | 0x2e4 | 32 | Cache Data Storage (mid-upper word), array offset: 0x204, array step: index*0x40, index2*0x10 | ||
ab_DATAW3S2ML | 0x2e8 | 32 | Cache Data Storage (mid-lower word), array offset: 0x208, array step: index*0x40, index2*0x10 | ||
ab_DATAW3S2LM | 0x2ec | 32 | Cache Data Storage (lowermost word), array offset: 0x20C, array step: index*0x40, index2*0x10 | ||
ab_DATAW3S3UM | 0x2f0 | 32 | Cache Data Storage (uppermost word), array offset: 0x200, array step: index*0x40, index2*0x10 | ||
ab_DATAW3S3MU | 0x2f4 | 32 | Cache Data Storage (mid-upper word), array offset: 0x204, array step: index*0x40, index2*0x10 | ||
ab_DATAW3S3ML | 0x2f8 | 32 | Cache Data Storage (mid-lower word), array offset: 0x208, array step: index*0x40, index2*0x10 | ||
ab_DATAW3S3LM | 0x2fc | 32 | Cache Data Storage (lowermost word), array offset: 0x20C, array step: index*0x40, index2*0x10 |
Table 3: Publicly available platforms using peripheral 'KinetisFMC'