Name | Type | Must Be Connected | Description |
---|---|---|---|
Reset | input | F (False) |
Table : Net Ports
Name | Type | Must Be Connected | Description |
---|---|---|---|
Reset | input | F (False) |
Table 1: Bus Slave Port: bport1
Name | Size (bytes) | Must Be Connected | Description |
---|---|---|---|
bport1 | 0x1000 | F (False) |
Table 2: Bus Slave Port: bport1 Registers:
Name | Offset | Width (bits) | Description | R/W | is Volatile |
---|---|---|---|---|---|
ab_SC | 0x0 | 32 | Status and Control Register, offset: 0x0 | ||
ab_MOD | 0x4 | 32 | Modulus Register, offset: 0x4 | ||
ab_CNT | 0x8 | 32 | Counter Register, offset: 0x8 | ||
ab_IDLY | 0xc | 32 | Interrupt Delay Register, offset: 0xC | ||
ab_CH0C1 | 0x10 | 32 | Channel n Control Register 1, array offset: 0x10, array step: 0x28 | ||
ab_CH0S | 0x14 | 32 | Channel n Status Register, array offset: 0x14, array step: 0x28 | ||
ab_CH0DLY0 | 0x18 | 32 | Channel n Delay 0 Register..Channel n Delay 1 Register, array offset: 0x18, array step: index*0x28, index2*0x4 | ||
ab_CH0DLY1 | 0x1c | 32 | Channel n Delay 0 Register..Channel n Delay 1 Register, array offset: 0x18, array step: index*0x28, index2*0x4 | ||
ab_CH1C1 | 0x38 | 32 | Channel n Control Register 1, array offset: 0x10, array step: 0x28 | ||
ab_CH1S | 0x3c | 32 | Channel n Status Register, array offset: 0x14, array step: 0x28 | ||
ab_CH1DLY0 | 0x40 | 32 | Channel n Delay 0 Register..Channel n Delay 1 Register, array offset: 0x18, array step: index*0x28, index2*0x4 | ||
ab_CH1DLY1 | 0x44 | 32 | Channel n Delay 0 Register..Channel n Delay 1 Register, array offset: 0x18, array step: index*0x28, index2*0x4 | ||
ab_CH2C1 | 0x60 | 32 | Channel n Control Register 1, array offset: 0x10, array step: 0x28 | ||
ab_CH2S | 0x64 | 32 | Channel n Status Register, array offset: 0x14, array step: 0x28 | ||
ab_CH2DLY0 | 0x68 | 32 | Channel n Delay 0 Register..Channel n Delay 1 Register, array offset: 0x18, array step: index*0x28, index2*0x4 | ||
ab_CH2DLY1 | 0x6c | 32 | Channel n Delay 0 Register..Channel n Delay 1 Register, array offset: 0x18, array step: index*0x28, index2*0x4 | ||
ab_CH3C1 | 0x88 | 32 | Channel n Control Register 1, array offset: 0x10, array step: 0x28 | ||
ab_CH3S | 0x8c | 32 | Channel n Status Register, array offset: 0x14, array step: 0x28 | ||
ab_CH3DLY0 | 0x90 | 32 | Channel n Delay 0 Register..Channel n Delay 1 Register, array offset: 0x18, array step: index*0x28, index2*0x4 | ||
ab_CH3DLY1 | 0x94 | 32 | Channel n Delay 0 Register..Channel n Delay 1 Register, array offset: 0x18, array step: index*0x28, index2*0x4 | ||
ab_DACINTC0 | 0x150 | 32 | DAC Interval Trigger n Control Register, array offset: 0x150, array step: 0x8 | ||
ab_DACINT0 | 0x154 | 32 | DAC Interval n Register, array offset: 0x154, array step: 0x8 | ||
ab_DACINTC1 | 0x158 | 32 | DAC Interval Trigger n Control Register, array offset: 0x150, array step: 0x8 | ||
ab_DACINT1 | 0x15c | 32 | DAC Interval n Register, array offset: 0x154, array step: 0x8 | ||
ab_POEN | 0x190 | 32 | Pulse-Out n Enable Register, offset: 0x190 | ||
ab_PO0DLY | 0x194 | 32 | Pulse-Out n Delay Register, array offset: 0x194, array step: 0x4 | ||
ab_PO1DLY | 0x198 | 32 | Pulse-Out n Delay Register, array offset: 0x194, array step: 0x4 | ||
ab_PO2DLY | 0x19c | 32 | Pulse-Out n Delay Register, array offset: 0x194, array step: 0x4 | ||
ab_PO3DLY | 0x1a0 | 32 | Pulse-Out n Delay Register, array offset: 0x194, array step: 0x4 |
Table 3: Publicly available platforms using peripheral 'KinetisPDB'