Name | Type | Must Be Connected | Description |
---|---|---|---|
Reset | input | F (False) |
Table : Net Ports
Name | Type | Must Be Connected | Description |
---|---|---|---|
Reset | input | F (False) |
Table 1: Bus Slave Port: bport1
Name | Size (bytes) | Must Be Connected | Description |
---|---|---|---|
bport1 | 0x2000 | F (False) |
Table 2: Bus Slave Port: bport1 Registers:
Name | Offset | Width (bits) | Description | R/W | is Volatile |
---|---|---|---|---|---|
ab_SOPT1 | 0x0 | 32 | System Options Register 1, offset: 0x0 | ||
ab_SOPT1CFG | 0x4 | 32 | SOPT1 Configuration Register, offset: 0x4 | ||
ab_SOPT2 | 0x1004 | 32 | System Options Register 2, offset: 0x1004 | ||
ab_SOPT4 | 0x100c | 32 | System Options Register 4, offset: 0x100C | ||
ab_SOPT5 | 0x1010 | 32 | System Options Register 5, offset: 0x1010 | ||
ab_SOPT6 | 0x1014 | 32 | System Options Register 6, offset: 0x1014 | ||
ab_SOPT7 | 0x1018 | 32 | System Options Register 7, offset: 0x1018 | ||
ab_SDID | 0x1024 | 32 | System Device Identification Register, offset: 0x1024 | ||
ab_SCGC1 | 0x1028 | 32 | System Clock Gating Control Register 1, offset: 0x1028 | ||
ab_SCGC2 | 0x102c | 32 | System Clock Gating Control Register 2, offset: 0x102C | ||
ab_SCGC3 | 0x1030 | 32 | System Clock Gating Control Register 3, offset: 0x1030 | ||
ab_SCGC4 | 0x1034 | 32 | System Clock Gating Control Register 4, offset: 0x1034 | ||
ab_SCGC5 | 0x1038 | 32 | System Clock Gating Control Register 5, offset: 0x1038 | ||
ab_SCGC6 | 0x103c | 32 | System Clock Gating Control Register 6, offset: 0x103C | ||
ab_SCGC7 | 0x1040 | 32 | System Clock Gating Control Register 7, offset: 0x1040 | ||
ab_CLKDIV1 | 0x1044 | 32 | System Clock Divider Register 1, offset: 0x1044 | ||
ab_CLKDIV2 | 0x1048 | 32 | System Clock Divider Register 2, offset: 0x1048 | ||
ab_FCFG1 | 0x104c | 32 | Flash Configuration Register 1, offset: 0x104C | ||
ab_FCFG2 | 0x1050 | 32 | Flash Configuration Register 2, offset: 0x1050 | ||
ab_UIDH | 0x1054 | 32 | Unique Identification Register High, offset: 0x1054 | ||
ab_UIDMH | 0x1058 | 32 | Unique Identification Register Mid-High, offset: 0x1058 | ||
ab_UIDML | 0x105c | 32 | Unique Identification Register Mid Low, offset: 0x105C | ||
ab_UIDL | 0x1060 | 32 | Unique Identification Register Low, offset: 0x1060 | ||
ab_CLKDIV4 | 0x1068 | 32 | System Clock Divider Register 4, offset: 0x1068 | ||
ab_MCR | 0x106c | 32 | Misc Control Register, offset: 0x106C |
Table 3: Publicly available platforms using peripheral 'KinetisSIM'