Name | Offset | Width (bits) | Description | R/W | is Volatile |
---|
ab_BDH | 0x0 | 8 | UART Baud Rate Registers:High, offset: 0x0 | | |
ab_BDL | 0x1 | 8 | UART Baud Rate Registers: Low, offset: 0x1 | | |
ab_C1 | 0x2 | 8 | UART Control Register 1, offset: 0x2 | | |
ab_C2 | 0x3 | 8 | UART Control Register 2, offset: 0x3 | | |
ab_S1 | 0x4 | 8 | UART Status Register 1, offset: 0x4 | | |
ab_S2 | 0x5 | 8 | UART Status Register 2, offset: 0x5 | | |
ab_C3 | 0x6 | 8 | UART Control Register 3, offset: 0x6 | | |
ab_D | 0x7 | 8 | UART Data Register, offset: 0x7 | | |
ab_MA1 | 0x8 | 8 | UART Match Address Registers 1, offset: 0x8 | | |
ab_MA2 | 0x9 | 8 | UART Match Address Registers 2, offset: 0x9 | | |
ab_C4 | 0xa | 8 | UART Control Register 4, offset: 0xA | | |
ab_C5 | 0xb | 8 | UART Control Register 5, offset: 0xB | | |
ab_ED | 0xc | 8 | UART Extended Data Register, offset: 0xC | | |
ab_MODEM | 0xd | 8 | UART Modem Register, offset: 0xD | | |
ab_IR | 0xe | 8 | UART Infrared Register, offset: 0xE | | |
ab_PFIFO | 0x10 | 8 | UART FIFO Parameters, offset: 0x10 | | |
ab_CFIFO | 0x11 | 8 | UART FIFO Control Register, offset: 0x11 | | |
ab_SFIFO | 0x12 | 8 | UART FIFO Status Register, offset: 0x12 | | |
ab_TWFIFO | 0x13 | 8 | UART FIFO Transmit Watermark, offset: 0x13 | | |
ab_TCFIFO | 0x14 | 8 | UART FIFO Transmit Count, offset: 0x14 | | |
ab_RWFIFO | 0x15 | 8 | UART FIFO Receive Watermark, offset: 0x15 | | |
ab_RCFIFO | 0x16 | 8 | UART FIFO Receive Count, offset: 0x16 | | |
ab_C7816 | 0x18 | 8 | UART 7816 Control Register, offset: 0x18 | | |
ab_IE7816 | 0x19 | 8 | UART 7816 Interrupt Enable Register, offset: 0x19 | | |
ab_IS7816 | 0x1a | 8 | UART 7816 Interrupt Status Register, offset: 0x1A | | |
ab_WP7816T0 | 0x1b | 8 | UART 7816 Wait Parameter Register, offset: 0x1B | | |
ab_WN7816 | 0x1c | 8 | UART 7816 Wait N Register, offset: 0x1C | | |
ab_WF7816 | 0x1d | 8 | UART 7816 Wait FD Register, offset: 0x1D | | |
ab_ET7816 | 0x1e | 8 | UART 7816 Error Threshold Register, offset: 0x1E | | |
ab_TL7816 | 0x1f | 8 | UART 7816 Transmit Length Register, offset: 0x1F | | |
ab_C6 | 0x21 | 8 | UART CEA709.1-B Control Register 6, offset: 0x21 | | |
ab_PCTH | 0x22 | 8 | UART CEA709.1-B Packet Cycle Time Counter High, offset: 0x22 | | |
ab_PCTL | 0x23 | 8 | UART CEA709.1-B Packet Cycle Time Counter Low, offset: 0x23 | | |
ab_B1T | 0x24 | 8 | UART CEA709.1-B Beta1 Timer, offset: 0x24 | | |
ab_SDTH | 0x25 | 8 | UART CEA709.1-B Secondary Delay Timer High, offset: 0x25 | | |
ab_SDTL | 0x26 | 8 | UART CEA709.1-B Secondary Delay Timer Low, offset: 0x26 | | |
ab_PRE | 0x27 | 8 | UART CEA709.1-B Preamble, offset: 0x27 | | |
ab_TPL | 0x28 | 8 | UART CEA709.1-B Transmit Packet Length, offset: 0x28 | | |
ab_IE | 0x29 | 8 | UART CEA709.1-B Interrupt Enable Register, offset: 0x29 | | |
ab_WB | 0x2a | 8 | UART CEA709.1-B WBASE, offset: 0x2A | | |
ab_S3 | 0x2b | 8 | UART CEA709.1-B Status Register, offset: 0x2B | | |
ab_S4 | 0x2c | 8 | UART CEA709.1-B Status Register, offset: 0x2C | | |
ab_RPL | 0x2d | 8 | UART CEA709.1-B Received Packet Length, offset: 0x2D | | |
ab_RPREL | 0x2e | 8 | UART CEA709.1-B Received Preamble Length, offset: 0x2E | | |
ab_CPW | 0x2f | 8 | UART CEA709.1-B Collision Pulse Width, offset: 0x2F | | |
ab_RIDT | 0x30 | 8 | UART CEA709.1-B Receive Indeterminate Time, offset: 0x30 | | |
ab_TIDT | 0x31 | 8 | UART CEA709.1-B Transmit Indeterminate Time, offset: 0x31 | | |