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FreescaleKinetisUART



OVP Peripheral Model: FreescaleKinetisUART



Model Specific Information

This page provides introductory usage information for an Imperas OVP peripheral behavioral model. The page is split into sections providing specific information for this peripheral, including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.

Description

Model of the UART peripheral used on the Freescale Kinetis platform

Limitations

Provides the base behaviour for the OVP Freescale Kinetis platforms

Reference

www.freescale.com/Kinetis

Licensing

Open Source Apache 2.0

Location

The KinetisUART peripheral model is located in an Imperas/OVP installation at the VLNV: freescale.ovpworld.org / peripheral / KinetisUART / 1.0.



Peripheral Instance Parameters

This model accepts the following parameters:

Table : Peripheral Parameters

NameTypeDescription
directReadWriteboolEnable the use of the DirectRead and DirectWrite connections
fifoSizeuns32Size of fifos (default 128)
moduleClkFrequns32Frequency (in hertz) of module clock used in baud rate calculation (default=10.2 MHz)
consoleboolIf specified, port number is ignored, and a console pops up automatically
portnumuns32If set, listen on this port. If set to zero, allocate a port from the pool and listen on that.
infilestringName of file to use for device source
outfilestringName of file to write device output
portFilestringIf portnum was specified as zero, write the port number to this file when it's known
logboolIf specified, serial output will go to simulator log
finishOnDisconnectboolIf set, disconnecting the port will cause the simulation to finish
connectnonblockingboolIf set, simulation can begin before the connection is made
xcharsuns32Width of console in characters
ycharsuns32Height of console in characters
recordstringRecord external events into this file
replaystringReplay external events from this file



Net Ports

This model has the following net ports:

Table 1: Net Ports

NameTypeMust Be ConnectedDescription
DirectWriteoutputF (False)
DirectReadinputF (False)
InterruptoutputF (False)
ResetinputF (False)



Bus Slave Ports

This model has the following bus slave ports:

Bus Slave Port: bport1

Table 2: Bus Slave Port: bport1

NameSize (bytes)Must Be ConnectedDescription
bport10x1000F (False)

Table 3: Bus Slave Port: bport1 Registers:

NameOffsetWidth (bits)DescriptionR/Wis Volatile
ab_BDH0x08UART Baud Rate Registers:High, offset: 0x0
ab_BDL0x18UART Baud Rate Registers: Low, offset: 0x1
ab_C10x28UART Control Register 1, offset: 0x2
ab_C20x38UART Control Register 2, offset: 0x3
ab_S10x48UART Status Register 1, offset: 0x4
ab_S20x58UART Status Register 2, offset: 0x5
ab_C30x68UART Control Register 3, offset: 0x6
ab_D0x78UART Data Register, offset: 0x7
ab_MA10x88UART Match Address Registers 1, offset: 0x8
ab_MA20x98UART Match Address Registers 2, offset: 0x9
ab_C40xa8UART Control Register 4, offset: 0xA
ab_C50xb8UART Control Register 5, offset: 0xB
ab_ED0xc8UART Extended Data Register, offset: 0xC
ab_MODEM0xd8UART Modem Register, offset: 0xD
ab_IR0xe8UART Infrared Register, offset: 0xE
ab_PFIFO0x108UART FIFO Parameters, offset: 0x10
ab_CFIFO0x118UART FIFO Control Register, offset: 0x11
ab_SFIFO0x128UART FIFO Status Register, offset: 0x12
ab_TWFIFO0x138UART FIFO Transmit Watermark, offset: 0x13
ab_TCFIFO0x148UART FIFO Transmit Count, offset: 0x14
ab_RWFIFO0x158UART FIFO Receive Watermark, offset: 0x15
ab_RCFIFO0x168UART FIFO Receive Count, offset: 0x16
ab_C78160x188UART 7816 Control Register, offset: 0x18
ab_IE78160x198UART 7816 Interrupt Enable Register, offset: 0x19
ab_IS78160x1a8UART 7816 Interrupt Status Register, offset: 0x1A
ab_WP7816T00x1b8UART 7816 Wait Parameter Register, offset: 0x1B
ab_WN78160x1c8UART 7816 Wait N Register, offset: 0x1C
ab_WF78160x1d8UART 7816 Wait FD Register, offset: 0x1D
ab_ET78160x1e8UART 7816 Error Threshold Register, offset: 0x1E
ab_TL78160x1f8UART 7816 Transmit Length Register, offset: 0x1F
ab_C60x218UART CEA709.1-B Control Register 6, offset: 0x21
ab_PCTH0x228UART CEA709.1-B Packet Cycle Time Counter High, offset: 0x22
ab_PCTL0x238UART CEA709.1-B Packet Cycle Time Counter Low, offset: 0x23
ab_B1T0x248UART CEA709.1-B Beta1 Timer, offset: 0x24
ab_SDTH0x258UART CEA709.1-B Secondary Delay Timer High, offset: 0x25
ab_SDTL0x268UART CEA709.1-B Secondary Delay Timer Low, offset: 0x26
ab_PRE0x278UART CEA709.1-B Preamble, offset: 0x27
ab_TPL0x288UART CEA709.1-B Transmit Packet Length, offset: 0x28
ab_IE0x298UART CEA709.1-B Interrupt Enable Register, offset: 0x29
ab_WB0x2a8UART CEA709.1-B WBASE, offset: 0x2A
ab_S30x2b8UART CEA709.1-B Status Register, offset: 0x2B
ab_S40x2c8UART CEA709.1-B Status Register, offset: 0x2C
ab_RPL0x2d8UART CEA709.1-B Received Packet Length, offset: 0x2D
ab_RPREL0x2e8UART CEA709.1-B Received Preamble Length, offset: 0x2E
ab_CPW0x2f8UART CEA709.1-B Collision Pulse Width, offset: 0x2F
ab_RIDT0x308UART CEA709.1-B Receive Indeterminate Time, offset: 0x30
ab_TIDT0x318UART CEA709.1-B Transmit Indeterminate Time, offset: 0x31



Platforms that use this peripheral component

Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.

Table 4: Publicly available platforms using peripheral 'KinetisUART'

Platform NameVendor
FreescaleKinetis60freescale.ovpworld.org
FreescaleKinetis64freescale.ovpworld.org



FreescalePeripherals
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