OVP Peripheral Model: FreescaleVybridI2C
Model Specific Information
This page provides introductory usage information for an Imperas OVP peripheral behavioral model.
The page is split into sections providing specific information for this peripheral,
including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.
Description
Model of the I2C peripheral used on the Freescale Vybrid platform
Limitations
Provides the base behaviour for the OVP Freescale Vybrid platforms
Reference
Development based on document number: VYBRIDRM Rev. 5, 07/2013
Licensing
Open Source Apache 2.0
Location
The VybridI2C peripheral model is located in an Imperas/OVP installation at the VLNV: freescale.ovpworld.org / peripheral / VybridI2C / 1.0.
Net Ports
This model has the following net ports:
Table : Net Ports
Name | Type | Must Be Connected | Description |
---|
Reset | input | F (False) | |
Bus Slave Ports
This model has the following bus slave ports:
Bus Slave Port: bport1
Table 1: Bus Slave Port: bport1
Name | Size (bytes) | Must Be Connected | Description |
---|
bport1 | 0x1000 | F (False) | |
Table 2: Bus Slave Port: bport1 Registers:
Name | Offset | Width (bits) | Description | R/W | is Volatile |
---|
ab_IBAD | 0x0 | 8 | I2C Bus Address Register, offset: 0x0 | | |
ab_IBFD | 0x1 | 8 | I2C Bus Frequency Divider Register, offset: 0x1 | | |
ab_IBCR | 0x2 | 8 | I2C Bus Control Register, offset: 0x2 | | |
ab_IBSR | 0x3 | 8 | I2C Bus Status Register, offset: 0x3 | | |
ab_IBDR | 0x4 | 8 | I2C Bus Data I/O Register, offset: 0x4 | | |
ab_IBIC | 0x5 | 8 | I2C Bus Interrupt Config Register, offset: 0x5 | | |
ab_IBDBG | 0x6 | 8 | I2C Bus Debug Register, offset: 0x6 | | |
Platforms that use this peripheral component
Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.
Table 3: Publicly available platforms using peripheral 'VybridI2C'