OVP Peripheral Model: FreescaleVybridSDHC
Model Specific Information
This page provides introductory usage information for an Imperas OVP peripheral behavioral model.
The page is split into sections providing specific information for this peripheral,
including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.
Description
Model of the SDHC peripheral used on the Freescale Vybrid platform
Limitations
Provides the base behaviour for the OVP Freescale Vybrid platforms
Reference
Development based on document number: VYBRIDRM Rev. 5, 07/2013
Licensing
Open Source Apache 2.0
Location
The VybridSDHC peripheral model is located in an Imperas/OVP installation at the VLNV: freescale.ovpworld.org / peripheral / VybridSDHC / 1.0.
Net Ports
This model has the following net ports:
Table : Net Ports
Name | Type | Must Be Connected | Description |
---|
Reset | input | F (False) | |
Bus Slave Ports
This model has the following bus slave ports:
Bus Slave Port: bport1
Table 1: Bus Slave Port: bport1
Name | Size (bytes) | Must Be Connected | Description |
---|
bport1 | 0x1000 | F (False) | |
Table 2: Bus Slave Port: bport1 Registers:
Name | Offset | Width (bits) | Description | R/W | is Volatile |
---|
ab_DSADDR | 0x0 | 32 | DMA System Address Register, offset: 0x0 | | |
ab_BLKATTR | 0x4 | 32 | Block Attributes Register, offset: 0x4 | | |
ab_CMDARG | 0x8 | 32 | Command Argument Register, offset: 0x8 | | |
ab_XFERTYP | 0xc | 32 | Transfer Type Register, offset: 0xC | | |
ab_CMDRSP0 | 0x10 | 32 | Command Response 0, offset: 0x10, array step: 0x4 | | |
ab_CMDRSP1 | 0x14 | 32 | Command Response 1, offset: 0x10, array step: 0x4 | | |
ab_CMDRSP2 | 0x18 | 32 | Command Response 2, offset: 0x10, array step: 0x4 | | |
ab_CMDRSP3 | 0x1c | 32 | Command Response 3, offset: 0x10, array step: 0x4 | | |
ab_DATPORT | 0x20 | 32 | Buffer Data Port Register, offset: 0x20 | | |
ab_PRSSTAT | 0x24 | 32 | Present State Register, offset: 0x24 | | |
ab_PROCTL | 0x28 | 32 | Protocol Control Register, offset: 0x28 | | |
ab_SYSCTL | 0x2c | 32 | System Control Register, offset: 0x2C | | |
ab_IRQSTAT | 0x30 | 32 | Interrupt Status Register, offset: 0x30 | | |
ab_IRQSTATEN | 0x34 | 32 | Interrupt Status Enable Register, offset: 0x34 | | |
ab_IRQSIGEN | 0x38 | 32 | Interrupt Signal Enable Register, offset: 0x38 | | |
ab_AC12ERR | 0x3c | 32 | Auto CMD12 Error Status Register, offset: 0x3C | | |
ab_HTCAPBLT | 0x40 | 32 | Host Controller Capabilities, offset: 0x40 | | |
ab_WML | 0x44 | 32 | Watermark Level Register, offset: 0x44 | | |
ab_FEVT | 0x50 | 32 | Force Event Register, offset: 0x50 | | |
ab_ADMAES | 0x54 | 32 | ADMA Error Status Register, offset: 0x54 | | |
ab_ADSADDR | 0x58 | 32 | ADMA System Address Register, offset: 0x58 | | |
ab_VENDOR | 0xc0 | 32 | Vendor Specific Register, offset: 0xC0 | | |
ab_MMCBOOT | 0xc4 | 32 | MMC Boot Register, offset: 0xC4 | | |
ab_HOSTVER | 0xfc | 32 | Host Controller Version, offset: 0xFC | | |
Platforms that use this peripheral component
Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.
Table 3: Publicly available platforms using peripheral 'VybridSDHC'