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IntelPciIDE



OVP Peripheral Model: IntelPciIDE



Model Specific Information

This page provides introductory usage information for an Imperas OVP peripheral behavioral model. The page is split into sections providing specific information for this peripheral, including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.

Licensing

Open Source Apache 2.0

Description

PCI:IDE interface. This forms part of the 82371 PIIX4 chip. It implements 4 IDE interfaces and 2 DMA controllers.

Limitations

This model has sufficient functionality to allow a Linux Kernel to Boot on the MIPS:MALTA platform.

Reference

Intel 82371EB South Bridge Chipset Datasheet

Location

The PciIDE peripheral model is located in an Imperas/OVP installation at the VLNV: intel.ovpworld.org / peripheral / PciIDE / 1.0.



Peripheral Instance Parameters

This model accepts the following parameters:

Table : Peripheral Parameters

NameTypeDescription
PCIslotuns32Specify which PCI slot the device occupies.
PCIfunctionuns32Specify which PCI function:code the device implements.
Drive0NamestringVirtual disk file for IDE channel 0
Drive0DeltastringDelta file for IDE channel 0. This feature is incomplete.
Drive1NamestringVirtual disk file for IDE channel 1
Drive1DeltastringDelta file for IDE channel 1. This feature is incomplete.
Drive2NamestringVirtual disk file for IDE channel 2
Drive2DeltastringDelta file for IDE channel 2. This feature is incomplete.
Drive3NamestringVirtual disk file for IDE channel 3
Drive3DeltastringDelta file for IDE channel 3. This feature is incomplete.
endianstringSet the system endian, "big" or "little"; used for writing boot code. Default is "little" endian.
recordstringRecord external events into this file
replaystringReplay external events from this file



Net Ports

This model has the following net ports:

Table 1: Net Ports

NameTypeMust Be ConnectedDescription
intOut0outputF (False)
intOut1outputF (False)



Bus Master Ports

This model has the following bus master ports:

Bus Master Port: dmaPort

Table 2: dmaPort

NameAddress Width (bits)Description
dmaPort32PCI DMA bus connection.



Bus Slave Ports

This model has the following bus slave ports:

Bus Slave Port: busPort

Table 3: Bus Slave Port: busPort

NameSize (bytes)Must Be ConnectedDescription
busPort0x8T (True)PCI main bus connection for register access.


No address blocks have been defined for this slave port.

Bus Slave Port: PCIconfig

Table 4: Bus Slave Port: PCIconfig

NameSize (bytes)Must Be ConnectedDescription
PCIconfig0x800F (False)PCI configuration bus connection.


No address blocks have been defined for this slave port.



Platforms that use this peripheral component

Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.

Table 5: Publicly available platforms using peripheral 'PciIDE'

Platform NameVendor
HeteroArmNucleusMIPSLinuximperas.ovpworld.org
MipsMaltamips.ovpworld.org
MipsMaltamips.ovpworld.org



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