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MicrosemiCoreUARTapb

OVP Peripheral Model: MicrosemiCoreUARTapb

Model Specific Information

This page provides introductory usage information for an Imperas OVP peripheral behavioral model. The page is split into sections providing specific information for this peripheral, including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.

Licensing

Open Source Apache 2.0

Description

Microsemi CoreUARTapb

Limitations

Basic functionality for transmit and receive

Reference

CoreUARTapb handbook v5.2 https://www.microsemi.com/document-portal/doc_view/130958-coreuartapb-handbook

Location

The CoreUARTapb peripheral model is located in an Imperas/OVP installation at the VLNV: microsemi.ovpworld.org / peripheral / CoreUARTapb / 1.0.

Peripheral Instance Parameters

This model accepts the following parameters:

Table : Peripheral Parameters

Name	Type	Description
console	bool	If specified, port number is ignored, and a console pops up automatically
client	bool	If true, model is a client and will connect to portnum. If false, model is a server and will listen on portnum.
portnum	uns32	If set, listen on, or connect to, this port. If set to zero in listen mode, allocate a port from the pool and listen on that.
hostname	string	Name (or IP address) of host to connect to. Valid if listen=true
infile	string	Name of file to use for device source
outfile	string	Name of file to write device output
portFile	string	If portnum was specified as zero, write the port number to this file when it's known
log	bool	If specified, serial output will go to simulator log
finishOnDisconnect	bool	If set, disconnecting the port will cause the simulation to finish
connectnonblocking	bool	If set, simulation can begin before the connection is made
xchars	uns32	Width of console in characters
ychars	uns32	Height of console in characters
record	string	Record external events into this file
replay	string	Replay external events from this file

Bus Slave Ports

This model has the following bus slave ports:

Bus Slave Port: port0

Table 1: Bus Slave Port: port0

Name	Size (bytes)	Must Be Connected	Description
port0	0x18	F (False)

Table 2: Bus Slave Port: port0 Registers:

Name	Offset	Width (bits)	Description	R/W	is Volatile
Reg_TxData	0x0	32
Reg_RxData	0x4	32
Reg_Ctrl1	0x8	32
Reg_Ctrl2	0xc	32
Reg_Status	0x10	32
Reg_Ctrl3	0x14	32

Platforms that use this peripheral component

Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.

Table 3: Publicly available platforms using peripheral 'CoreUARTapb'

Platform Name	Vendor
RiscvRV32FreeRTOS	imperas.ovpworld.org

MicrosemiPeripherals

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