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Mips34Kf

Model Information


This page provides detailed information about the OVP Fast Processor Model of the MIPS 34Kf core.
Processor IP owner is MIPS. More information is available from them here.

OVP Fast Processor Model is written in C.
Provides a C API for use in C based platforms.
Provides a native C++ interface for use in SystemC TLM2 platforms.

The model is written using the OVP VMI API that provides a Virtual Machine Interface that defines the behavior of the processor.
The VMI API makes a clear line between model and simulator allowing very good optimization and world class high speed performance.

The model is provided as a binary shared object and is also available as source (different models have different licensing conditions). This allows the download and use of the model binary or the use of the source to explore and modify the model.

The model has been run through an extensive QA and regression testing process.

Parallel Simulation using Imperas QuantumLeap


Traditionally, processor models and simulators make use of one thread on the host PC. Imperas have developed a technology, called QuantumLeap, that makes use of the many host cores found in modern PC/workstations to achieve industry leading simulation performance. To find out about the Imperas parallel simulation lookup Imperas QuantumLeap. There are videos of QuantumLeap on ARM here, and MIPS here. For press information related to QuantumLeap for ARM click here or for MIPS click here.
Many of the OVP Fast Processor Models have been qualified to work with QuantumLeap - this is indicated for this model below.

Embedded Software Development tools


This model executes instructions of the target architecture and provides an interface for debug access. An interface to GDB is provided and this allows the connection of many industry standard debuggers that use the GDB/RSP interface. For more information watch the OVP video here.
The model also works with the Imperas Multicore Debugger and advanced Verification, Analysis and Profiling tools.

Instruction Set Simulator (ISS) for MIPS 34Kf


An ISS is a software development tool that takes in instructions for a target processor and executes them. The heart of an ISS is the model of the processor. Imperas has developed a range of ISS products for use in embedded software development that utilize this fast Fast Processor Model. The Imperas MIPS 34Kf ISS runs on Windows/Linux x86 systems and takes a cross compiled elf file of your program and allows very fast execution. The MIPS 34Kf ISS also provides access to standard GDB/RSP debuggers and connects to the Eclipse IDE and Imperas debuggers.

Overview of MIPS 34Kf Fast Processor Model


Model Variant name: 34Kf
Description:
    MIPS32 Configurable Processor Model
Licensing:
    Usage of binary model under license governing simulator usage. Source of model available under Imperas Software License Agreement.
Limitations:
    If this model is not part of your installation, then it is available for download from www.OVPworld.org/MIPSuser.
Verification:
    Models have been validated correct as part of the MIPS Verified program and run through the MIPS AVP test programs
Features:
    only MIPS32 Instruction set implemented
    MMU Type: Standard TLB
    FPU implemented
    L1 I and D cache model in either full or tag-only mode implemented (disabled by default)
    Vectored interrupts implemented
    MIPS16e ASE implemented
    MT ASE implemented
    DSP ASE implemented

Model downloadable (needs registration and to be logged in) in package mips32.model for Windows32 and for Linux32
OVP simulator downloadable (needs registration and to be logged in) in package OVPsim for Windows32 and for Linux32
OVP Download page here.
OVP documentation that provides overview information on processor models is available OVP_Guide_To_Using_Processor_Models.pdf.

Full model specific documentation on the variant 34Kf is available OVP_Model_Specific_Information_mips32_r1r5_34Kf.pdf.

Configuration


Location: The Fast Processor Model source and object file is found in the installation VLNV tree: mips.ovpworld.org/processor/mips32_r1r5/1.0
Processor Endian-ness: This model can be set to either endian-ness (normally by a pin, or the ELF code).
Processor ELF Code: The ELF code for this model is: 0x8
QuantumLeap Support: The processor model is qualified to run in a QuantumLeap enabled simulator.

TLM Initiator Ports (Bus Ports)

Port TypeNameWidth (bits)Description
masterINSTRUCTION12
masterDATA12

SystemC Signal Ports (Net Ports)

Port TypeNameDescription
yqinput
yq0input
yq1input
yq2input
yq3input
yq4input
yq5input
yq6input
yq7input
yq8input
yq9input
yq10input
yq11input
yq12input
yq13input
yq14input
yq15input
resetinput
dintinput
SI_UseExceptionBaseinput
SI_ExceptionBaseinput
hwint0_VPE0input
hwint1_VPE0input
hwint2_VPE0input
hwint3_VPE0input
hwint4_VPE0input
hwint5_VPE0input
nmi_VPE0input
hwint0input
vc_run_VPE0input
hwint0_VPE1input
hwint1_VPE1input
hwint2_VPE1input
hwint3_VPE1input
hwint4_VPE1input
hwint5_VPE1input
nmi_VPE1input
vc_run_VPE1input

No FIFO Ports in 34Kf.


Exceptions

NameCodeDescription
Int0
Mod1
TLBL2
TLBS3
AdEL4
AdES5
IBE6
DBE7
Sys8
Bp9
RI10
CpU11
Ov12
Tr13
FPE15
Impl116
Impl217
C2E18
TLBRI19
TLBXI20
MDMX22
WATCH23
MCheck24
Thread25
DSPDis26
Prot29
CacheErr30

Execution Modes

ModeCodeDescription
KERNEL0
DEBUG1
SUPERVISOR2
USER3

More Detailed Information

The 34Kf OVP Fast Processor Model also has parameters, model commands, and many registers.
The model may also have hierarchy or be multicore and have other attributes and capabilities.
To see this information, please have a look at the model variant specific documents.
Click here to see the detailed document OVP_Model_Specific_Information_mips32_r1r5_34Kf.pdf.

Other Sites/Pages with similar information

Information on the 34Kf OVP Fast Processor Model can also be found on other web sites:
www.imperas.com has more information on the model library.



MipsProcessors
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