LIBRARY  |  COMPANIES |   PLATFORMS |   PROCESSORS |   PERIPHERALS
NxpIMX6_GPIO



OVP Peripheral Model: NxpIMX6_GPIO



Model Specific Information

This page provides introductory usage information for an Imperas OVP peripheral behavioral model. The page is split into sections providing specific information for this peripheral, including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.

Description

NXP i.MX6 GPIO

Licensing

Open Source Apache 2.0

Limitations

No behaviour is implemented.

Reference

i.MX 6Solo/6DualLite Applications Processor Reference Manual (IMX6SDLRM_Ref_Manual.pdf

Location

The iMX6_GPIO peripheral model is located in an Imperas/OVP installation at the VLNV: nxp.ovpworld.org / peripheral / iMX6_GPIO / 1.0.



Bus Slave Ports

This model has the following bus slave ports:

Bus Slave Port: bport1

Table : Bus Slave Port: bport1

NameSize (bytes)Must Be ConnectedDescription
bport10x4000T (True)

Table 1: Bus Slave Port: bport1 Registers:

NameOffsetWidth (bits)DescriptionR/Wis Volatile
ab_DR0x032GPIO Data Register
ab_GDIR0x432GPIO Direction Register
ab_PSR0x832GPIO PAD Status Register
ab_ICR10xc32GPIO interrupt configuration register1
ab_ICR20x1032GPIO interrupt configuration register2
ab_IMR10x1432GPIO interrupt mask register
ab_ISR0x1832GPIO interrupt status register
ab_EDGE_SEL0x1c32GPIO edge select register



Platforms that use this peripheral component

Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.

Table 2: Publicly available platforms using peripheral 'iMX6_GPIO'

Platform NameVendor
iMX6Snxp.ovpworld.org



NxpPeripherals
Page was generated in 0.0182 seconds