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PpcM440

Model Information


This page provides detailed information about the OVP Fast Processor Model of the POWER m440 core.
Processor IP owner is IBM. More information is available from them here.

OVP Fast Processor Model is written in C.
Provides a C API for use in C based platforms.
Provides a native C++ interface for use in SystemC TLM2 platforms.

The model is written using the OVP VMI API that provides a Virtual Machine Interface that defines the behavior of the processor.
The VMI API makes a clear line between model and simulator allowing very good optimization and world class high speed performance.

The model is provided as a binary shared object and is also available as source (different models have different licensing conditions). This allows the download and use of the model binary or the use of the source to explore and modify the model.

The model has been run through an extensive QA and regression testing process.

Parallel Simulation using Imperas QuantumLeap


Traditionally, processor models and simulators make use of one thread on the host PC. Imperas have developed a technology, called QuantumLeap, that makes use of the many host cores found in modern PC/workstations to achieve industry leading simulation performance. To find out about the Imperas parallel simulation lookup Imperas QuantumLeap. There are videos of QuantumLeap on ARM here, and MIPS here. For press information related to QuantumLeap for ARM click here or for MIPS click here.
Many of the OVP Fast Processor Models have been qualified to work with QuantumLeap - this is indicated for this model below.

Embedded Software Development tools


This model executes instructions of the target architecture and provides an interface for debug access. An interface to GDB is provided and this allows the connection of many industry standard debuggers that use the GDB/RSP interface. For more information watch the OVP video here.
The model also works with the Imperas Multicore Debugger and advanced Verification, Analysis and Profiling tools.

Instruction Set Simulator (ISS) for POWER m440


An ISS is a software development tool that takes in instructions for a target processor and executes them. The heart of an ISS is the model of the processor. Imperas has developed a range of ISS products for use in embedded software development that utilize this fast Fast Processor Model. The Imperas POWER m440 ISS runs on Windows/Linux x86 systems and takes a cross compiled elf file of your program and allows very fast execution. The POWER m440 ISS also provides access to standard GDB/RSP debuggers and connects to the Eclipse IDE and Imperas debuggers.

Overview of POWER m440 Fast Processor Model


Model Variant name: m440
Description:
    PPC32 Family Processor Model. Providing PPC 400 family variants.
Licensing:
    Open Source Apache 2.0
Limitations:
    This model is currently under development
    The FPU is incomplete
    FPU exceptions are not implemented
    Some Single Floating Point FPU instructions are not implemented
    The MMU is not implemented
Verification:
    Basic verification of ISA against golden reference has been performed
Features:
    

Model downloadable (needs registration and to be logged in) in package powerpc32.model for Windows32 and for Linux32
OVP simulator downloadable (needs registration and to be logged in) in package OVPsim for Windows32 and for Linux32
OVP Download page here.
OVP documentation that provides overview information on processor models is available OVP_Guide_To_Using_Processor_Models.pdf.

Full model specific documentation on the variant m440 is available OVP_Model_Specific_Information_powerpc32_400_m440.pdf.

Configuration


Location: The Fast Processor Model source and object file is found in the installation VLNV tree: power.ovpworld.org/processor/powerpc32_400/1.0
Processor Endian-ness: This model can be set to either endian-ness (normally by a pin, or the ELF code).
Processor ELF Code: The ELF code for this model is: 0x14
QuantumLeap Support: The processor model is qualified to run in a QuantumLeap enabled simulator.

TLM Initiator Ports (Bus Ports)

Port TypeNameWidth (bits)Description
masterINSTRUCTION32
masterDATA32

SystemC Signal Ports (Net Ports)

Port TypeNameDescription
resetinput

No FIFO Ports in m440.


Exceptions

NameCodeDescription
Reset0
Undefined1
Arith2
RdAlign3
WrAlign4
RdAbort5
WrAbort6
RdPriv7
WrPriv8
Fetch9

No Execution Modes in m440.


More Detailed Information

The m440 OVP Fast Processor Model also has parameters, model commands, and many registers.
The model may also have hierarchy or be multicore and have other attributes and capabilities.
To see this information, please have a look at the model variant specific documents.
Click here to see the detailed document OVP_Model_Specific_Information_powerpc32_400_m440.pdf.

Other Sites/Pages with similar information

Information on the m440 OVP Fast Processor Model can also be found on other web sites:
www.imperas.com has more information on the model library.



PowerPCProcessors
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