OVP Peripheral Model: RenesasDma
Model Specific Information
This page provides introductory usage information for an Imperas OVP peripheral behavioral model.
The page is split into sections providing specific information for this peripheral,
including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.
Licensing
Open Source Apache 2.0
Description
Renesas DMA Controller
Limitations
Initial implementation to support CAN DMA message transfer only
Reference
R01UH0128ED0700, Rev. 7.00, Oct 06, 2010
Location
The dma peripheral model is located in an Imperas/OVP installation at the VLNV: renesas.ovpworld.org / peripheral / dma / 1.0.
Net Ports
This model has the following net ports:
Table : Net Ports
Name | Type | Must Be Connected | Description |
---|
INTDMA0 | output | F (False) | |
INTDMA1 | output | F (False) | |
INTDMA2 | output | F (False) | |
INTDMA3 | output | F (False) | |
INTDMA4 | output | F (False) | |
INTDMA5 | output | F (False) | |
INTDMA6 | output | F (False) | |
INTDMA7 | output | F (False) | |
INTDMA8 | output | F (False) | |
INTDMA9 | output | F (False) | |
DMA0EN | output | F (False) | |
DMA1EN | output | F (False) | |
ADDMARQ0 | input | F (False) | |
ADDMARQ1 | input | F (False) | |
INTTS0CD | input | F (False) | |
INTTS1CD | input | F (False) | |
INTCE0C | input | F (False) | |
INTCE1C | input | F (False) | |
INTBE0R | input | F (False) | |
INTBE1R | input | F (False) | |
INTUC0R | input | F (False) | |
INTUC1R | input | F (False) | |
INTUC2R | input | F (False) | |
Bus Master Ports
This model has the following bus master ports:
Bus Master Port: DMAPM
Table 1: DMAPM
Name | Address Width (bits) | Description |
---|
DMAPM | 28 | |
Bus Slave Ports
This model has the following bus slave ports:
Bus Slave Port: DMAP0
Table 2: Bus Slave Port: DMAP0
Name | Size (bytes) | Must Be Connected | Description |
---|
DMAP0 | 0x10 | F (False) | |
Table 3: Bus Slave Port: DMAP0 Registers:
Name | Offset | Width (bits) | Description | R/W | is Volatile |
---|
abc_DMAWC0 | 0x0 | 16 | DMA Controller Wait Control Register 0 | | |
abc_DMAWC1 | 0x2 | 16 | DMA Controller Wait Control Register 1 | | |
Bus Slave Port: DMAP1
Table 4: Bus Slave Port: DMAP1
Name | Size (bytes) | Must Be Connected | Description |
---|
DMAP1 | 0x100 | F (False) | |
Table 5: Bus Slave Port: DMAP1 Registers:
Name | Offset | Width (bits) | Description | R/W | is Volatile |
---|
abw_MAR0 | 0x0 | 16 | DMA Controller Transfer Memory Start Address Register | | |
abw_MAR1 | 0x2 | 16 | DMA Controller Transfer Memory Start Address Register | | |
abw_MAR2 | 0x4 | 16 | DMA Controller Transfer Memory Start Address Register | | |
abw_MAR3 | 0x6 | 16 | DMA Controller Transfer Memory Start Address Register | | |
abw_MAR4 | 0x8 | 16 | DMA Controller Transfer Memory Start Address Register | | |
abw_MAR5 | 0xa | 16 | DMA Controller Transfer Memory Start Address Register | | |
abw_MAR6 | 0xc | 16 | DMA Controller Transfer Memory Start Address Register | | |
abw_MAR7 | 0xe | 16 | DMA Controller Transfer Memory Start Address Register | | |
abw_MAR8 | 0x10 | 16 | DMA Controller Transfer Memory Start Address Register | | |
abw_MAR9 | 0x12 | 16 | DMA Controller Transfer Memory Start Address Register | | |
abb_SAR2 | 0x24 | 8 | DMA Controller Transfer SFR Start Adrress Register | | |
abb_SAR3 | 0x25 | 8 | DMA Controller Transfer SFR Start Adrress Register | | |
abb_DTFR4 | 0x80 | 8 | DMA Controller Trigger Factor register | | |
abb_DTFR5 | 0x81 | 8 | DMA Controller Trigger Factor register | | |
abb_DTFR6 | 0x82 | 8 | DMA Controller Trigger Factor register | | |
abb_DTFR7 | 0x83 | 8 | DMA Controller Trigger Factor register | | |
abb_DTCR0 | 0x40 | 8 | DMA Controller Transfer Count register | | |
abb_DTCR1 | 0x41 | 8 | DMA Controller Transfer Count register | | |
abb_DTCR2 | 0x42 | 8 | DMA Controller Transfer Count register | | |
abb_DTCR3 | 0x43 | 8 | DMA Controller Transfer Count register | | |
abb_DTCR4 | 0x44 | 8 | DMA Controller Transfer Count register | | |
abb_DTCR5 | 0x45 | 8 | DMA Controller Transfer Count register | | |
abb_DTCR6 | 0x46 | 8 | DMA Controller Transfer Count register | | |
abb_DTCR7 | 0x47 | 8 | DMA Controller Transfer Count register | | |
abb_DTCR8 | 0x48 | 8 | DMA Controller Transfer Count register | | |
abb_DTCR9 | 0x49 | 8 | DMA Controller Transfer Count register | | |
abb_DMASL | 0x62 | 8 | DMA Controller Status Register | | |
abb_DMAMCL | 0x60 | 8 | DMA Controller Mode Control Register | | |
abb_DMADSCL | 0x64 | 8 | DMA Controller Data Size Control Register | | |
Platforms that use this peripheral component
Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.
Table 6: Publicly available platforms using peripheral 'dma'