Model Information

This page provides detailed information about the OVP Fast Processor Model of the Renesas RH850G3M core.
Processor IP owner is Renesas (formerly NEC). More information is available from them here.

OVP Fast Processor Model is written in C.
Provides a C API for use in C based platforms.
Provides a native C++ interface for use in SystemC TLM2 platforms.

The model is written using the OVP VMI API that provides a Virtual Machine Interface that defines the behavior of the processor.
The VMI API makes a clear line between model and simulator allowing very good optimization and world class high speed performance.

The model is provided as a binary shared object and is also available as source (different models have different licensing conditions). This allows the download and use of the model binary or the use of the source to explore and modify the model.

The model has been run through an extensive QA and regression testing process.

Parallel Simulation using Imperas QuantumLeap

Traditionally, processor models and simulators make use of one thread on the host PC. Imperas have developed a technology, called QuantumLeap, that makes use of the many host cores found in modern PC/workstations to achieve industry leading simulation performance. To find out about the Imperas parallel simulation lookup Imperas QuantumLeap. There are videos of QuantumLeap on ARM here, and MIPS here. For press information related to QuantumLeap for ARM click here or for MIPS click here.
Many of the OVP Fast Processor Models have been qualified to work with QuantumLeap - this is indicated for this model below.

Embedded Software Development tools

This model executes instructions of the target architecture and provides an interface for debug access. An interface to GDB is provided and this allows the connection of many industry standard debuggers that use the GDB/RSP interface. For more information watch the OVP video here.
The model also works with the Imperas Multicore Debugger and advanced Verification, Analysis and Profiling tools.

Instruction Set Simulator (ISS) for Renesas RH850G3M

An ISS is a software development tool that takes in instructions for a target processor and executes them. The heart of an ISS is the model of the processor. Imperas has developed a range of ISS products for use in embedded software development that utilize this fast Fast Processor Model. The Imperas Renesas RH850G3M ISS runs on Windows/Linux x86 systems and takes a cross compiled elf file of your program and allows very fast execution. The Renesas RH850G3M ISS also provides access to standard GDB/RSP debuggers and connects to the Eclipse IDE and Imperas debuggers.

Overview of Renesas RH850G3M Fast Processor Model

Model Variant name: RH850G3M
Description:
    RH850 Family Processor Model.
    Reference Document : RH850G3M Rev 1.00, Aug. 2014
Licensing:
    Open Source Apache 2.0
Limitations:
    No FPU Exceptions
Verification:
    Models have been extensively tested by Imperas, In addition Verification suites have been supplied by Renesas for Feature Set validation
Features:
    RH850 Support for MPU
    RH850 Vector based Exceptions.
    RH850 Integer Instructions.
    RH850 Floating Point Instructions.
    Supervisor & User Execution Modes

Model downloadable (needs registration and to be logged in) in package rh850.model for Windows32 and for Linux32
OVP simulator downloadable (needs registration and to be logged in) in package OVPsim for Windows32 and for Linux32
OVP Download page here.
OVP documentation that provides overview information on processor models is available OVP_Guide_To_Using_Processor_Models.pdf.

Full model specific documentation on the variant RH850G3M is available OVP_Model_Specific_Information_rh850_RH850G3M.pdf.

Configuration

Location: The Fast Processor Model source and object file is found in the installation VLNV tree: renesas.ovpworld.org/processor/rh850/1.0
Processor Endian-ness: This model is little endian.
Processor ELF Code: The ELF code for this model is: 0x57
QuantumLeap Support: The processor model is qualified to run in a QuantumLeap enabled simulator.

TLM Initiator Ports (Bus Ports)

SystemC Signal Ports (Net Ports)

No FIFO Ports in RH850G3M.

Exceptions

Execution Modes

More Detailed Information

The RH850G3M OVP Fast Processor Model also has parameters, model commands, and many registers.
The model may also have hierarchy or be multicore and have other attributes and capabilities.
To see this information, please have a look at the model variant specific documents.
Click here to see the detailed document OVP_Model_Specific_Information_rh850_RH850G3M.pdf.

Other Sites/Pages with similar information

Information on the RH850G3M OVP Fast Processor Model can also be found on other web sites:
www.imperas.com has more information on the model library.