Renesas RL78 Processor Model RenesasRL78
The Renesas RL78 processor model developed by eSOL TRINITY will be released as part of the standard packages.
This page provides detailed information about the OVP Fast Processor Model of the Renesas RL78 core.
Processor IP owner is Renesas. More information is available from them here.∞
OVP Fast Processor Model is written in C.
Provides a C API for use in C based platforms.
Provides a native C+\+ interface for use in SystemC TLM2 platforms.
The model is written using the OVP VMI API that provides a Virtual Machine Interface that defines the behavior of the processor.
The VMI API makes a clear line between model and simulator allowing very good optimization and world class high speed performance.
Here is an example platform that models the RL78/G14 Renesas Demonstration Kit (RDK). It contains six peripherals. These peripherals do not implement full functionality and are only for demonstration purpose.
- rl78_intc - Interrupt Controller
- rl78_port - GPIO Port
- rl78_timer - Timer
- rl78_uart - UART
- st7579 - LCD Controller connect via SPI and GPIO
- rl78_sys - psuedo registers
Some demo applications also are included.
- blink_R5F104LJ - Toggle Port output with interval timer interrupt.
- lifegame_R5F104PJ - LCD demonstration
Overview of Renesas RL78 Fast Processor Model
|Example Platform and demo application|
example_rl78.zip / 1.63 MB
Model Variant name:
RL78 Family Processor Model.
Open Source Apache 2.0
The following register are non-functional
PMC (Processor mode control register)
Models have been extensively tested by ESOL Trinity.
All RL78 Instructions are supported.
RL78-S3 core : All instructions are supported. Register bank is supported
RL78-S2 core : 6 instructions (MULU, MULHU, MULH, DIVHU, DIVWU, MACHU, MACH) are not supported. Register bank is supported
RL78-S1 core : 7 instructions (above 6 instruction and SEL) are not supported. Register bank is also not supported
RL78 Family User’s Manual: Software Rev.2.20 Nov 2014 (r01us0015ej0220_rl78)
RL78ファミリ ユーザーズマニュアル ソフトウェア編 Rev.2.20 2014.11 (r01us0015jj0220_rl78)
Location: The Fast Processor Model source and object file is found in the installation VLNV tree:
Processor Endian-ness: This model is little endian.
Processor ELF Code: The ELF code for this model is: 0xC5 (EM_RL78)
QuantumLeap Support: The processor model has not yet been qualified to run in a QuantumLeap enabled simulator.
||Reset port. When asserted, read program start address from 00000h, and jump to this address.
||External interrupt port
||Interrupt acknowledge port
No FIFO Ports in rl78.
More Detailed Information
||Illegal instruction exception (will reset)
||Illegal address exception (will reset)
||External interrupt request
The rl78 OVP Fast Processor Model also has parameters, model commands, and many registers.
The model may also have hierarchy or be multicore and have other attributes and capabilities.
To see this information, please have a look at the model variant specific documents.
Click here to see the detailed document OVP_Model_Specific_Information_rl78_RL78-S3.pdf.