OVP Peripheral Model: RenesasUPD70F3441Logic
Model Specific Information
This page provides introductory usage information for an Imperas OVP peripheral behavioral model.
The page is split into sections providing specific information for this peripheral,
including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.
Licensing
Open Source Apache 2.0
Description
Renesas V850PHO3 / UPD70F3441 Glue Logic
Limitations
No known limitations
Reference
R01UH0128ED0700, Rev. 7.00, Oct 06, 2010
Location
The UPD70F3441Logic peripheral model is located in an Imperas/OVP installation at the VLNV: renesas.ovpworld.org / peripheral / UPD70F3441Logic / 1.0.
Net Ports
This model has the following net ports:
Table : Net Ports
Name | Type | Must Be Connected | Description |
---|
NMIIN | input | F (False) | |
INTDEDF | input | F (False) | |
INTDEDR | input | F (False) | |
INTDEDFR | input | F (False) | |
INTOSD | input | F (False) | |
INTP4 | input | F (False) | |
INTUC0R | input | F (False) | |
INTP5 | input | F (False) | |
INTUC1R | input | F (False) | |
INTBRG0 | input | F (False) | |
INTBRG1 | input | F (False) | |
INTCB0T | input | F (False) | |
INTUC2T | input | F (False) | |
INTCB0R | input | F (False) | |
INTUC2R | input | F (False) | |
INTP13 | input | F (False) | |
INTCB0RE | input | F (False) | |
INTUC2RE | input | F (False) | |
INTDMA3 | input | F (False) | |
INTFL | input | F (False) | |
NMIOUT | output | F (False) | |
INT0 | output | F (False) | |
INT1 | output | F (False) | |
INT6 | output | F (False) | |
INT7 | output | F (False) | |
INT75 | output | F (False) | |
INT99 | output | F (False) | |
INT100 | output | F (False) | |
INT101 | output | F (False) | |
INT116 | output | F (False) | |
Bus Slave Ports
This model has the following bus slave ports:
Bus Slave Port: LOGICP0
Table 1: Bus Slave Port: LOGICP0
Name | Size (bytes) | Must Be Connected | Description |
---|
LOGICP0 | 0x4 | F (False) | |
Table 2: Bus Slave Port: LOGICP0 Registers:
Name | Offset | Width (bits) | Description | R/W | is Volatile |
---|
reg0_INTSEL | 0x0 | 8 | | | |
reg0_INTERRF | 0x2 | 8 | | | |
Bus Slave Port: LOGICP1
Table 3: Bus Slave Port: LOGICP1
Name | Size (bytes) | Must Be Connected | Description |
---|
LOGICP1 | 0x76 | F (False) | |
Table 4: Bus Slave Port: LOGICP1 Registers:
Name | Offset | Width (bits) | Description | R/W | is Volatile |
---|
reg0_LOGICP0 | 0x0 | 8 | | | |
reg0_P1 | 0x2 | 8 | | | |
reg0_PM1 | 0x22 | 8 | | | |
reg0_PMC1 | 0x42 | 8 | | | |
reg0_P2 | 0x4 | 8 | | | |
reg0_PM2 | 0x24 | 8 | | | |
reg0_PMC2 | 0x44 | 8 | | | |
reg0_P3 | 0x6 | 8 | | | |
reg0_PM3 | 0x26 | 8 | | | |
reg0_PMC3 | 0x46 | 8 | | | |
reg0_P4 | 0x8 | 8 | | | |
reg0_PM4 | 0x28 | 8 | | | |
reg0_PMC4 | 0x48 | 8 | | | |
reg0_P5 | 0xa | 8 | | | |
reg0_PM5 | 0x2a | 8 | | | |
reg0_PMC5 | 0x4a | 8 | | | |
reg0_P6 | 0xc | 8 | | | |
reg0_PM6 | 0x2c | 8 | | | |
reg0_PMC6 | 0x4c | 8 | | | |
reg0_P7 | 0xe | 8 | | | |
reg0_PM7 | 0x2e | 8 | | | |
reg0_PMC7 | 0x4e | 8 | | | |
reg0_P8 | 0x10 | 8 | | | |
reg0_PM8 | 0x30 | 8 | | | |
reg0_PMC8 | 0x50 | 8 | | | |
reg0_P9 | 0x12 | 8 | | | |
reg0_PM9 | 0x32 | 8 | | | |
reg0_PMC9 | 0x52 | 8 | | | |
reg0_P10 | 0x14 | 8 | | | |
reg0_PM10 | 0x34 | 8 | | | |
reg0_PMC10 | 0x54 | 8 | | | |
reg0_P11 | 0x16 | 8 | | | |
reg0_PM11 | 0x36 | 8 | | | |
reg0_PMC11 | 0x56 | 8 | | | |
reg0_PFC1 | 0x62 | 8 | | | |
reg0_PFC2 | 0x64 | 8 | | | |
reg0_PFC4 | 0x68 | 8 | | | |
reg0_PFC7 | 0x6e | 8 | | | |
reg0_PFC8 | 0x70 | 8 | | | |
reg0_PFC9 | 0x72 | 8 | | | |
reg0_PFC10 | 0x74 | 8 | | | |
Bus Slave Port: LOGICP2
Table 5: Bus Slave Port: LOGICP2
Name | Size (bytes) | Must Be Connected | Description |
---|
LOGICP2 | 0xc | F (False) | |
Table 6: Bus Slave Port: LOGICP2 Registers:
Name | Offset | Width (bits) | Description | R/W | is Volatile |
---|
reg0_PESC5 | 0x0 | 8 | | | |
reg0_ESOST5 | 0x2 | 8 | | | |
reg0_PESC6 | 0x4 | 8 | | | |
reg0_ESOST6 | 0x6 | 8 | | | |
reg0_PESMK5 | 0x8 | 8 | | | |
reg0_PESMK6 | 0xa | 8 | | | |
Bus Slave Port: LOGICP3
Table 7: Bus Slave Port: LOGICP3
Name | Size (bytes) | Must Be Connected | Description |
---|
LOGICP3 | 0x1 | F (False) | |
Table 8: Bus Slave Port: LOGICP3 Registers:
Name | Offset | Width (bits) | Description | R/W | is Volatile |
---|
reg0_PRCMD | 0x0 | 8 | | | |
Platforms that use this peripheral component
Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.
Table 9: Publicly available platforms using peripheral 'UPD70F3441Logic'