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RiscvPLIC



OVP Peripheral Model: RiscvPLIC



Model Specific Information

This page provides introductory usage information for an Imperas OVP peripheral behavioral model. The page is split into sections providing specific information for this peripheral, including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.

Licensing

Open Source Apache 2.0

Description

PLIC Interrupt Controller

Limitations

Sufficient functionality to boot Virtio BusyBear Linux Kernel. The num_priorities parameter is currently ignored. All 32 bits of priority registers are supported.

Reference

The RISC-V Instruction Set Manual Volume II: Privileged Architecture Version 1.10 (https://riscv.org/specifications/privileged-isa)

SiFive Freedom U540-C000 Manual FU540-C000-v1.0.pdf (https://www.sifive.com/documentation/chips/freedom-u540-c000-manual)

Location

The PLIC peripheral model is located in an Imperas/OVP installation at the VLNV: riscv.ovpworld.org / peripheral / PLIC / 1.0.



Peripheral Instance Parameters

This model accepts the following parameters:

Table : Peripheral Parameters

NameTypeDescription
num_sourcesuns32Number of Input Interrupt Sources
num_targetsuns32Number of Output Interrupt Targets, Hart/Context
num_prioritiesuns32Number of Priority levels
priority_baseuns32Base Address offset for Priority Registers
pending_baseuns32Base Address offset for Pending Registers
enable_baseuns32Base Address offset for Enable Registers
enable_strideuns32Stride size for Enable Register Block
context_baseuns32Base Address offset for Context Registers, Threshold/Claim
context_strideuns32Stride size for Context Register Block



Net Ports

This model has the following net ports:

Table 1: Net Ports

NameTypeMust Be ConnectedDescription
irqS1inputF (False)
irqT0outputF (False)



Bus Slave Ports

This model has the following bus slave ports:

Bus Slave Port: port0

Table 2: Bus Slave Port: port0

NameSize (bytes)Must Be ConnectedDescription
port00x4000000F (False)

Table 3: Bus Slave Port: port0 Registers:

NameOffsetWidth (bits)DescriptionR/Wis Volatile
Priority00x032Priority of Input Interrupt Source 0
Priority10x432Priority of Input Interrupt Source 1
Pending00x100032Pending Interrupt Register for Interrupts 31 downto 0
Target0_Enable00x200032Target Hart/Context 0 Enable for Interrupt Source 0
Target0_Enable10x200432Target Hart/Context 0 Enable for Interrupt Source 1
Target0_Enable20x200832Target Hart/Context 0 Enable for Interrupt Source 2
Target0_Enable30x200c32Target Hart/Context 0 Enable for Interrupt Source 3
Target0_Enable40x201032Target Hart/Context 0 Enable for Interrupt Source 4
Target0_Enable50x201432Target Hart/Context 0 Enable for Interrupt Source 5
Target0_Enable60x201832Target Hart/Context 0 Enable for Interrupt Source 6
Target0_Enable70x201c32Target Hart/Context 0 Enable for Interrupt Source 7
Target0_Enable80x202032Target Hart/Context 0 Enable for Interrupt Source 8
Target0_Enable90x202432Target Hart/Context 0 Enable for Interrupt Source 9
Target0_Enable100x202832Target Hart/Context 0 Enable for Interrupt Source 10
Target0_Enable110x202c32Target Hart/Context 0 Enable for Interrupt Source 11
Target0_Enable120x203032Target Hart/Context 0 Enable for Interrupt Source 12
Target0_Enable130x203432Target Hart/Context 0 Enable for Interrupt Source 13
Target0_Enable140x203832Target Hart/Context 0 Enable for Interrupt Source 14
Target0_Enable150x203c32Target Hart/Context 0 Enable for Interrupt Source 15
Target0_Enable160x204032Target Hart/Context 0 Enable for Interrupt Source 16
Target0_Enable170x204432Target Hart/Context 0 Enable for Interrupt Source 17
Target0_Enable180x204832Target Hart/Context 0 Enable for Interrupt Source 18
Target0_Enable190x204c32Target Hart/Context 0 Enable for Interrupt Source 19
Target0_Enable200x205032Target Hart/Context 0 Enable for Interrupt Source 20
Target0_Enable210x205432Target Hart/Context 0 Enable for Interrupt Source 21
Target0_Enable220x205832Target Hart/Context 0 Enable for Interrupt Source 22
Target0_Enable230x205c32Target Hart/Context 0 Enable for Interrupt Source 23
Target0_Enable240x206032Target Hart/Context 0 Enable for Interrupt Source 24
Target0_Enable250x206432Target Hart/Context 0 Enable for Interrupt Source 25
Target0_Enable260x206832Target Hart/Context 0 Enable for Interrupt Source 26
Target0_Enable270x206c32Target Hart/Context 0 Enable for Interrupt Source 27
Target0_Enable280x207032Target Hart/Context 0 Enable for Interrupt Source 28
Target0_Enable290x207432Target Hart/Context 0 Enable for Interrupt Source 29
Target0_Enable300x207832Target Hart/Context 0 Enable for Interrupt Source 30
Target0_Enable310x207c32Target Hart/Context 0 Enable for Interrupt Source 31
Target0_Threshold0x20000032Target Hart/Context 0 Priority Threshold
Target0_Claim0x20000432Target Hart/Context 0 Claim for Source



Platforms that use this peripheral component

Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.

Table 4: Publicly available platforms using peripheral 'PLIC'

Platform NameVendor
RiscvRV32FreeRTOSimperas.ovpworld.org
virtioriscv.ovpworld.org
FU540sifive.ovpworld.org
S51CCsifive.ovpworld.org



RiscVperipherals
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