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RiscvRV32FreeRTOS



OVP Virtual Platform: RiscvRV32FreeRTOS

This page provides detailed information about the OVP Virtual Platform Model of the imperas.ovpworld.org RiscvRV32FreeRTOS platform.

Licensing

Open Source Apache 2.0

Description

Example platform to instance RISCV RV32IM processor core. Peripherals and memory address layout to boot pre-compiled FreeRTOS operating system.

Reference

https://github.com/RISCV-on-Microsemi-FPGA/FreeRTOS/tree/master/FreeRTOS_on_Mi-V_Processor

Limitations

Created to executed the specific software

Location

The RiscvRV32FreeRTOS virtual platform is located in an Imperas/OVP installation at the VLNV: imperas.ovpworld.org / module / RiscvRV32FreeRTOS / 1.0.

Platform Summary

Table : Components in platform

TypeInstanceVendorComponent
Processorcpu0riscv.ovpworld.orgriscvRV32IM
Peripheraluart0microsemi.ovpworld.orgCoreUARTapb
Peripheralplic0riscv.ovpworld.orgPLIC
Peripheralprci0riscv.ovpworld.orgCLINT
Memorynvramovpworld.orgram
Memoryddrovpworld.orgram
Busbus0(builtin)address width:32

Platform Simulation Attributes

Table 1: Platform Simulation Attributes

AttributeValueDescription
stoponctrlcstoponctrlcStop on control-C



Processor [riscv.ovpworld.org/processor/riscv/1.0] instance: cpu0

Processor model type: 'riscv' variant 'RV32IM' definition

Imperas OVP processor models support multiple variants and details of the variants implemented in this model can be found in:
- the Imperas installation located at ImperasLib/source/riscv.ovpworld.org/processor/riscv/1.0/doc
- the OVP website: OVP_Model_Specific_Information_riscv_RV32IM.pdf

Description

RISC-V RV32IM 32-bit processor model

Licensing

This Model is released under the Open Source Apache 2.0

Extensions

The model has the following architectural extensions enabled, and the following bits in the misa CSR Extensions field will be set upon reset:
misa bit 8: RV32I/64I/128I base ISA
misa bit 12: extension M (integer multiply/divide instructions)
misa bit 18: extension S (Supervisor mode)
misa bit 20: extension U (User mode)
To specify features that can be dynamically enabled or disabled by writes to the misa register in addition to those listed above, use parameter "add_Extensions_mask". This is a string parameter containing the feature letters to add; for example, value "DV" indicates that double-precision floating point and the Vector Extension can be enabled or disabled by writes to the misa register.
Legacy parameter "misa_Extensions_mask" can also be used. This Uns32-valued parameter specifies all writable bits in the misa Extensions field, replacing any value defined in the base variant.
Note that any features that are indicated as present in the misa mask but absent in the misa will be ignored. See the next section.
Legacy parameter "misa_Extensions" can also be used. This Uns32-valued parameter specifies the reset value for the misa CSR Extensions field, replacing any value defined in the base variant.

Available (But Not Enabled) Extensions

The following extensions are supported by the model, but not enabled by default in this variant:
misa bit 0: extension A (atomic instructions) (NOT ENABLED)
misa bit 2: extension C (compressed instructions) (NOT ENABLED)
misa bit 3: extension D (double-precision floating point) (NOT ENABLED)
misa bit 4: RV32E base ISA (NOT ENABLED)
misa bit 5: extension F (single-precision floating point) (NOT ENABLED)
misa bit 13: extension N (user-level interrupts) (NOT ENABLED)
misa bit 21: extension V (vector instructions) (NOT ENABLED)
misa bit 23: extension X (non-standard extensions present) (NOT ENABLED)
To add features from this list to the base variant, use parameter "add_Extensions". This is a string parameter containing the feature letters to add; for example, value "DV" indicates that double-precision floating point and the Vector Extension should be enabled, if they are absent.

Features

On this variant, the Machine trap-vector base-address register (mtvec) is writable. It can instead be configured as read-only using parameter "mtvec_is_ro".
Values written to "mtvec" are masked using the value 0xfffffffd. A different mask of writable bits may be specified using parameter "mtvec_mask" if required. In addition, when Vectored interrupt mode is enabled, parameter "tvec_align" may be used to specify additional hardware-enforced base address alignment. In this variant, "tvec_align" defaults to 0, implying no alignment constraint.
The initial value of "mtvec" is 0x0. A different value may be specified using parameter "mtvec" if required.
Values written to "stvec" are masked using the value 0xfffffffd. A different mask of writable bits may be specified using parameter "stvec_mask" if required. parameter "tvec_align" may be used to specify additional hardware-enforced base address alignment in the same manner as for the "mtvec" register, described above.
On reset, the model will restart at address 0x0. A different reset address may be specified using parameter "reset_address" if required.
On an NMI, the model will restart at address 0x0. A different NMI address may be specified using parameter "nmi_address" if required.
WFI will halt the processor until an interrupt occurs. It can instead be configured as a NOP using parameter "wfi_is_nop". WFI timeout wait is implemented with a time limit of 0 (i.e. WFI causes an Illegal Instruction trap in Supervisor mode when mstatus.TW=1).
The "cycle" CSR is implemented in this variant. Set parameter "cycle_undefined" to True to instead specify that "cycle" is unimplemented and reads of it should trap to Machine mode.
The "time" CSR is implemented in this variant. Set parameter "time_undefined" to True to instead specify that "time" is unimplemented and reads of it should trap to Machine mode. Usually, the value of the "time" CSR should be provided by the platform - see notes below about the artifact "CSR" bus for information about how this is done.
The "instret" CSR is implemented in this variant. Set parameter "instret_undefined" to True to instead specify that "instret" is unimplemented and reads of it should trap to Machine mode.
A 9-bit ASID is implemented. Use parameter "ASID_bits" to specify a different implemented ASID size if required.
This variant supports address translation modes 0 and 1. Use parameter "Sv_modes" to specify a bit mask of different modes if required.
Unaligned memory accesses are not supported by this variant. Set parameter "unaligned" to "T" to enable such accesses.
16 PMP entries are implemented by this variant. Use parameter "PMP_registers" to specify a different number of PMP entries; set the parameter to 0 to disable the PMP unit. The PMP grain size (G) is 0, meaning that PMP regions as small as 4 bytes are implemented. Use parameter "PMP_grain" to specify a different grain size if required.

Interrupts

The "reset" port is an active-high reset input. The processor is halted when "reset" goes high and resumes execution from the reset address specified using the "reset_address" parameter when the signal goes low. The "mcause" register is cleared to zero.
The "nmi" port is an active-high NMI input. The processor is halted when "nmi" goes high and resumes execution from the address specified using the "nmi_address" parameter when the signal goes low. The "mcause" register is cleared to zero.
All other interrupt ports are active high.

Debug Mask

It is possible to enable model debug messages in various categories. This can be done statically using the "override_debugMask" parameter, or dynamically using the "debugflags" command. Enabled messages are specified using a bitmask value, as follows:
Value 0x002: enable debugging of PMP and virtual memory state;
Value 0x004: enable debugging of interrupt state.
All other bits in the debug bitmask are reserved and must not be set to non-zero values.

Integration Support

This model implements a number of non-architectural pseudo-registers and other features to facilitate integration.

CSR Register External Implementation

If parameter "enable_CSR_bus" is True, an artifact 16-bit bus "CSR" is enabled. Slave callbacks installed on this bus can be used to implement modified CSR behavior (use opBusSlaveNew or icmMapExternalMemory, depending on the client API). A CSR with index 0xABC is mapped on the bus at address 0xABC0; as a concrete example, implementing CSR "time" (number 0xC01) externally requires installation of callbacks at address 0xC010 on the CSR bus.

Limitations

Instruction pipelines are not modeled in any way. All instructions are assumed to complete immediately. This means that instruction barrier instructions (e.g. fence.i) are treated as NOPs, with the exception of any Illegal Instruction behavior, which is modeled.
Caches and write buffers are not modeled in any way. All loads, fetches and stores complete immediately and in order, and are fully synchronous. Data barrier instructions (e.g. fence) are treated as NOPs, with the exception of any Illegal Instruction behavior, which is modeled.
Real-world timing effects are not modeled: all instructions are assumed to complete in a single cycle.
Hardware Performance Monitor and Debug registers are not implemented and hardwired to zero.
The TLB is architecturally-accurate but not device accurate. This means that all TLB maintenance and address translation operations are fully implemented but the cache is larger than in the real device.

Verification

All instructions have been extensively tested by Imperas, using tests generated specifically for this model and also reference tests from https://github.com/riscv/riscv-tests.

References

The Model details are based upon the following specifications:
RISC-V Instruction Set Manual, Volume I: User-Level ISA (User Architecture Version 20190305-Base-Ratification)
RISC-V Instruction Set Manual, Volume II: Privileged Architecture (Privileged Architecture Version 20190405-Priv-MSU-Ratification)

Instance Parameters

Several parameters can be specified when a processor is instanced in a platform. For this processor instance 'cpu0' it has been instanced with the following parameters:

Table 2: Processor Instance 'cpu0' Parameters (Configurations)

ParameterValueDescription
simulateexceptionssimulateexceptionsCauses the processor simulate exceptions instead of halting
mips50The nominal MIPS for the processor

Table 3: Processor Instance 'cpu0' Parameters (Attributes)

Parameter NameValueType
variantRV32IMenum

Memory Map for processor 'cpu0' bus: 'bus0'

Processor instance 'cpu0' is connected to bus 'bus0' using master port 'INSTRUCTION'.

Processor instance 'cpu0' is connected to bus 'bus0' using master port 'DATA'.

Table 4: Memory Map ( 'cpu0' / 'bus0' [width: 32] )

Lo AddressHi AddressInstanceComponent
0x400000000x43FFFFFFplic0PLIC
0x440000000x4400BFFFprci0CLINT
0x600000000x6003FFFFnvramram
0x700010000x70001017uart0CoreUARTapb
0x800000000x8FFFFFFFddrram

Net Connections to processor: 'cpu0'

Table 5: Processor Net Connections ( 'cpu0' )

Net PortNetInstanceComponent
MExternalInterrupteipplic0PLIC
MTimerInterruptMTimerInterruptprci0CLINT
MSWInterruptMSWInterruptprci0CLINT



Peripheral Instances



Peripheral [microsemi.ovpworld.org/peripheral/CoreUARTapb/1.0] instance: uart0

Licensing

Open Source Apache 2.0

Description

Microsemi CoreUARTapb

Limitations

Basic functionality for transmit and receive

Reference

CoreUARTapb handbook v5.2 https://www.microsemi.com/document-portal/doc_view/130958-coreuartapb-handbook

There are no configuration options set for this peripheral instance.



Peripheral [riscv.ovpworld.org/peripheral/PLIC/1.0] instance: plic0

Licensing

Open Source Apache 2.0

Description

PLIC Interrupt Controller

Limitations

Sufficient functionality to boot Virtio BusyBear Linux Kernel. The num_priorities parameter is currently ignored. All 32 bits of priority registers are supported.

Reference

The RISC-V Instruction Set Manual Volume II: Privileged Architecture Version 1.10 (https://riscv.org/specifications/privileged-isa)
SiFive Freedom U540-C000 Manual FU540-C000-v1.0.pdf (https://www.sifive.com/documentation/chips/freedom-u540-c000-manual)

Table 6: Configuration options (attributes) set for instance 'plic0'

AttributesValue
num_sources256
num_targets1



Peripheral [riscv.ovpworld.org/peripheral/CLINT/1.0] instance: prci0

Licensing

Open Source Apache 2.0

Description

Risc-V Core Local Interruptor (CLINT). Use the num_harts parameter to specify the number of harts suported (default 1). For each supported hart there will be an MTimerInterruptN and MSWInterruptN net port, plus msipN and mtimecmpN registers implemented, where N is a value from 0..num_harts-1 There is also a single mtime register.

Limitations

Writes to mtime register are not supported

Reference

SiFive Freedom U540-C000 Manual FU540-C000-v1.0.pdf (https://www.sifive.com/documentation/chips/freedom-u540-c000-manual)

Table 7: Configuration options (attributes) set for instance 'prci0'

AttributesValue
clockMHz1.0



ImperasPlatforms RiscVplatforms
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