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S51CC



OVP Virtual Platform: S51CC

This page provides detailed information about the OVP Virtual Platform Model of the sifive.ovpworld.org S51CC platform.

Licensing

Open Source Apache 2.0

Description

SiFive S51 (aka E51) Core Complex module. To run a bare metal application use the --program command line option to specify an elf file to be loaded. It must be linked to use addresses corresponding to the implemented memory regions. The --program option will override the initial pc with the ELF file's start address.

Reference

SiFive S51 Core Complex Manual v19.02 (Downloaded from: https://www.sifive.com/documentation)

Limitations

Caches are not modeled. The Instruction Tightly Integrated Memory (ITIM) is implemented simply as RAM. Deallocation by writing to the byte immediately following the memory is a NOP. The Safe Zero Address area at address 0x0 is implemented as normal RAM, so is not guaranteed to always read as 0.

Location

The S51CC virtual platform is located in an Imperas/OVP installation at the VLNV: sifive.ovpworld.org / module / S51CC / 1.0.

Platform Summary

Table : Components in platform

TypeInstanceVendorComponent
ProcessorS51sifive.ovpworld.orgriscvS51
Peripheralclintriscv.ovpworld.orgCLINT
Peripheralplicriscv.ovpworld.orgPLIC
Memorysafe0addrovpworld.orgram
MemorydebugRAMovpworld.orgram
MemorydebugROMovpworld.orgrom
Memoryhart0ITIMovpworld.orgram
Memoryhart0DTIMovpworld.orgram
Busbus0(builtin)address width:40

Platform Simulation Attributes

Table 1: Platform Simulation Attributes

AttributeValueDescription
stoponctrlcstoponctrlcStop on control-C



External Ports for Module S51CC

Table 2: External Ports

Port TypePort NameInternal Connection
busportsystemPortbus0
netportgi1gi1
netportgi2gi2
netportgi3gi3
netportgi4gi4
netportgi5gi5
netportgi6gi6
netportgi7gi7
netportgi8gi8
netportgi9gi9
netportgi10gi10
netportgi11gi11
netportgi12gi12
netportgi13gi13
netportgi14gi14
netportgi15gi15
netportgi16gi16
netportgi17gi17
netportgi18gi18
netportgi19gi19
netportgi20gi20
netportgi21gi21
netportgi22gi22
netportgi23gi23
netportgi24gi24
netportgi25gi25
netportgi26gi26
netportgi27gi27
netportgi28gi28
netportgi29gi29
netportgi30gi30
netportgi31gi31
netportgi32gi32
netportgi33gi33
netportgi34gi34
netportgi35gi35
netportgi36gi36
netportgi37gi37
netportgi38gi38
netportgi39gi39
netportgi40gi40
netportgi41gi41
netportgi42gi42
netportgi43gi43
netportgi44gi44
netportgi45gi45
netportgi46gi46
netportgi47gi47
netportgi48gi48
netportgi49gi49
netportgi50gi50
netportgi51gi51
netportgi52gi52
netportgi53gi53
netportgi54gi54
netportgi55gi55
netportgi56gi56
netportgi57gi57
netportgi58gi58
netportgi59gi59
netportgi60gi60
netportgi61gi61
netportgi62gi62
netportgi63gi63
netportgi64gi64
netportgi65gi65
netportgi66gi66
netportgi67gi67
netportgi68gi68
netportgi69gi69
netportgi70gi70
netportgi71gi71
netportgi72gi72
netportgi73gi73
netportgi74gi74
netportgi75gi75
netportgi76gi76
netportgi77gi77
netportgi78gi78
netportgi79gi79
netportgi80gi80
netportgi81gi81
netportgi82gi82
netportgi83gi83
netportgi84gi84
netportgi85gi85
netportgi86gi86
netportgi87gi87
netportgi88gi88
netportgi89gi89
netportgi90gi90
netportgi91gi91
netportgi92gi92
netportgi93gi93
netportgi94gi94
netportgi95gi95
netportgi96gi96
netportgi97gi97
netportgi98gi98
netportgi99gi99
netportgi100gi100
netportgi101gi101
netportgi102gi102
netportgi103gi103
netportgi104gi104
netportgi105gi105
netportgi106gi106
netportgi107gi107
netportgi108gi108
netportgi109gi109
netportgi110gi110
netportgi111gi111
netportgi112gi112
netportgi113gi113
netportgi114gi114
netportgi115gi115
netportgi116gi116
netportgi117gi117
netportgi118gi118
netportgi119gi119
netportgi120gi120
netportgi121gi121
netportgi122gi122
netportgi123gi123
netportgi124gi124
netportgi125gi125
netportgi126gi126
netportgi127gi127
netportli0LocalInterrupt0
netportli1LocalInterrupt1
netportli2LocalInterrupt2
netportli3LocalInterrupt3
netportli4LocalInterrupt4
netportli5LocalInterrupt5
netportli6LocalInterrupt6
netportli7LocalInterrupt7
netportli8LocalInterrupt8
netportli9LocalInterrupt9
netportli10LocalInterrupt10
netportli11LocalInterrupt11
netportli12LocalInterrupt12
netportli13LocalInterrupt13
netportli14LocalInterrupt14
netportli15LocalInterrupt15
netportresetPortresetNet



Processor [sifive.ovpworld.org/processor/riscv/1.0] instance: S51

Processor model type: 'riscv' variant 'S51' definition

Imperas OVP processor models support multiple variants and details of the variants implemented in this model can be found in:
- the Imperas installation located at ImperasLib/source/sifive.ovpworld.org/processor/riscv/1.0/doc
- the OVP website: OVP_Model_Specific_Information_sifive_riscv_S51.pdf

Description

RISC-V S51 64-bit processor model

Licensing

This Model is released under the Open Source Apache 2.0

Extensions

The model has the following architectural extensions enabled, and the following bits in the misa CSR Extensions field will be set upon reset:
misa bit 0: extension A (atomic instructions)
misa bit 2: extension C (compressed instructions)
misa bit 8: RV32I/64I/128I base ISA
misa bit 12: extension M (integer multiply/divide instructions)
misa bit 20: extension U (User mode)
To specify features that can be dynamically enabled or disabled by writes to the misa register in addition to those listed above, use parameter "add_Extensions_mask". This is a string parameter containing the feature letters to add; for example, value "DV" indicates that double-precision floating point and the Vector Extension can be enabled or disabled by writes to the misa register.
Legacy parameter "misa_Extensions_mask" can also be used. This Uns32-valued parameter specifies all writable bits in the misa Extensions field, replacing any value defined in the base variant.
Note that any features that are indicated as present in the misa mask but absent in the misa will be ignored. See the next section.
Legacy parameter "misa_Extensions" can also be used. This Uns32-valued parameter specifies the reset value for the misa CSR Extensions field, replacing any value defined in the base variant.

Available (But Not Enabled) Extensions

The following extensions are supported by the model, but not enabled by default in this variant:
misa bit 3: extension D (double-precision floating point) (NOT ENABLED)
misa bit 4: RV32E base ISA (NOT ENABLED)
misa bit 5: extension F (single-precision floating point) (NOT ENABLED)
misa bit 13: extension N (user-level interrupts) (NOT ENABLED)
misa bit 18: extension S (Supervisor mode) (NOT ENABLED)
misa bit 21: extension V (vector instructions) (NOT ENABLED)
misa bit 23: extension X (non-standard extensions present) (NOT ENABLED)
To add features from this list to the base variant, use parameter "add_Extensions". This is a string parameter containing the feature letters to add; for example, value "DV" indicates that double-precision floating point and the Vector Extension should be enabled, if they are absent.

General Features

On this variant, the Machine trap-vector base-address register (mtvec) is writable. It can instead be configured as read-only using parameter "mtvec_is_ro".
Values written to "mtvec" are masked using the value 0x3ffffffffd. A different mask of writable bits may be specified using parameter "mtvec_mask" if required. In addition, when Vectored interrupt mode is enabled, parameter "tvec_align" may be used to specify additional hardware-enforced base address alignment. In this variant, "tvec_align" defaults to 64.
The initial value of "mtvec" is 0x0. A different value may be specified using parameter "mtvec" if required.
On reset, the model will restart at address 0x0. A different reset address may be specified using parameter "reset_address" if required.
On an NMI, the model will restart at address 0x0. A different NMI address may be specified using parameter "nmi_address" if required.
WFI will halt the processor until an interrupt occurs. It can instead be configured as a NOP using parameter "wfi_is_nop". WFI timeout wait is implemented with a time limit of 0 (i.e. WFI causes an Illegal Instruction trap in Supervisor mode when mstatus.TW=1).
The "cycle" CSR is implemented in this variant. Set parameter "cycle_undefined" to True to instead specify that "cycle" is unimplemented and reads of it should trap to Machine mode.
The "time" CSR is not implemented in this variant and reads of it will require emulation in Machine mode. Set parameter "time_undefined" to False to instead specify that "time" is implemented.
The "instret" CSR is implemented in this variant. Set parameter "instret_undefined" to True to instead specify that "instret" is unimplemented and reads of it should trap to Machine mode.
Unaligned memory accesses are not supported by this variant. Set parameter "unaligned" to "T" to enable such accesses.
Unaligned memory accesses are not supported for AMO instructions by this variant. Set parameter "unalignedAMO" to "T" to enable such accesses.
8 PMP entries are implemented by this variant. Use parameter "PMP_registers" to specify a different number of PMP entries; set the parameter to 0 to disable the PMP unit. The PMP grain size (G) is 0, meaning that PMP regions as small as 4 bytes are implemented. Use parameter "PMP_grain" to specify a different grain size if required.
LR/SC instructions are implemented with a 64-byte reservation granule. A different granule size may be specified using parameter "lr_sc_grain".

Interrupts

The "reset" port is an active-high reset input. The processor is halted when "reset" goes high and resumes execution from the reset address specified using the "reset_address" parameter when the signal goes low. The "mcause" register is cleared to zero.
The "nmi" port is an active-high NMI input. The processor is halted when "nmi" goes high and resumes execution from the address specified using the "nmi_address" parameter when the signal goes low. The "mcause" register is cleared to zero.
All other interrupt ports are active high.

Debug Mask

It is possible to enable model debug messages in various categories. This can be done statically using the "override_debugMask" parameter, or dynamically using the "debugflags" command. Enabled messages are specified using a bitmask value, as follows:
Value 0x002: enable debugging of PMP and virtual memory state;
Value 0x004: enable debugging of interrupt state.
All other bits in the debug bitmask are reserved and must not be set to non-zero values.

Integration Support

This model implements a number of non-architectural pseudo-registers and other features to facilitate integration.

CSR Register External Implementation

If parameter "enable_CSR_bus" is True, an artifact 16-bit bus "CSR" is enabled. Slave callbacks installed on this bus can be used to implement modified CSR behavior (use opBusSlaveNew or icmMapExternalMemory, depending on the client API). A CSR with index 0xABC is mapped on the bus at address 0xABC0; as a concrete example, implementing CSR "time" (number 0xC01) externally requires installation of callbacks at address 0xC010 on the CSR bus.

LR/SC Active Address

Artifact register "LRSCAddress" shows the active LR/SC lock address. The register holds all-ones if there is no LR/SC operation active.

Limitations

Instruction pipelines are not modeled in any way. All instructions are assumed to complete immediately. This means that instruction barrier instructions (e.g. fence.i) are treated as NOPs, with the exception of any Illegal Instruction behavior, which is modeled.
Caches and write buffers are not modeled in any way. All loads, fetches and stores complete immediately and in order, and are fully synchronous. Data barrier instructions (e.g. fence) are treated as NOPs, with the exception of any Illegal Instruction behavior, which is modeled.
Real-world timing effects are not modeled: all instructions are assumed to complete in a single cycle.
Hardware Performance Monitor and Debug registers are not implemented and hardwired to zero.

Verification

All instructions have been extensively tested by Imperas, using tests generated specifically for this model and also reference tests from https://github.com/riscv/riscv-tests.
Also reference tests have been used from various sources including:
https://github.com/riscv/riscv-tests
https://github.com/ucb-bar/riscv-torture
The Imperas OVPsim RISC-V models are used in the RISC-V FoundationsCompliance Framework as a functional Golden Reference:
https://github.com/riscv/riscv-compliance
where the simulated model is used to provide the reference signaturesfor compliance testing.The Imperas OVPsim RISC-V models are used as reference in both opensource and commercial instruction stream test generators for hardwaredesign verification, for example:
http://valtrix.in/sting/ from Valtrix
https://github.com/google/riscv-dv from Google
The Imperas OVPsim RISC-V models are also used by commercial and opensource RISC-V Core RTL developers as a reference to ensure correctfunctionality of their IP.

References

The Model details are based upon the following specifications:
RISC-V Instruction Set Manual, Volume I: User-Level ISA (User Architecture Version 20190305-Base-Ratification)
RISC-V Instruction Set Manual, Volume II: Privileged Architecture (Privileged Architecture Version 20190405-Priv-MSU-Ratification)
SiFive S51 (E51) Core Complex Manual v2p0

Instance Parameters

Several parameters can be specified when a processor is instanced in a platform. For this processor instance 'S51' it has been instanced with the following parameters:

Table 3: Processor Instance 'S51' Parameters (Configurations)

ParameterValueDescription
simulateexceptionssimulateexceptionsCauses the processor simulate exceptions instead of halting
mips1000The nominal MIPS for the processor

Table 4: Processor Instance 'S51' Parameters (Attributes)

Parameter NameValueType
variantS51enum
local_int_num16uns32

Memory Map for processor 'S51' bus: 'bus0'

Processor instance 'S51' is connected to bus 'bus0' using master port 'INSTRUCTION'.

Processor instance 'S51' is connected to bus 'bus0' using master port 'DATA'.

Table 5: Memory Map ( 'S51' / 'bus0' [width: 40] )

Lo AddressHi AddressInstanceComponent
0x00x7safe0addrram
0x3000x3FFdebugRAMram
0x8000xFFFdebugROMrom
0x20000000x200BFFFclintCLINT
0x80000000x8002000hart0ITIMram
0xC0000000xFFFFFFFplicPLIC
0x800000000x8000FFFFhart0DTIMram

Net Connections to processor: 'S51'

Table 6: Processor Net Connections ( 'S51' )

Net PortNetInstanceComponent
MTimerInterruptMTimerInterrupt0clintCLINT
MSWInterruptMSWInterrupt0clintCLINT
MExternalInterruptMExternalInterrupt0plicPLIC
LocalInterrupt0LocalInterrupt0unknown
LocalInterrupt1LocalInterrupt1unknown
LocalInterrupt2LocalInterrupt2unknown
LocalInterrupt3LocalInterrupt3unknown
LocalInterrupt4LocalInterrupt4unknown
LocalInterrupt5LocalInterrupt5unknown
LocalInterrupt6LocalInterrupt6unknown
LocalInterrupt7LocalInterrupt7unknown
LocalInterrupt8LocalInterrupt8unknown
LocalInterrupt9LocalInterrupt9unknown
LocalInterrupt10LocalInterrupt10unknown
LocalInterrupt11LocalInterrupt11unknown
LocalInterrupt12LocalInterrupt12unknown
LocalInterrupt13LocalInterrupt13unknown
LocalInterrupt14LocalInterrupt14unknown
LocalInterrupt15LocalInterrupt15unknown
resetresetNetunknown



Peripheral Instances



Peripheral [riscv.ovpworld.org/peripheral/CLINT/1.0] instance: clint

Licensing

Open Source Apache 2.0

Description

Risc-V Core Local Interruptor (CLINT). Use the num_harts parameter to specify the number of harts suported (default 1). For each supported hart there will be an MTimerInterruptN and MSWInterruptN net port, plus msipN and mtimecmpN registers implemented, where N is a value from 0..num_harts-1 There is also a single mtime register.

Limitations

Writes to mtime register are not supported

Reference

SiFive Freedom U540-C000 Manual FU540-C000-v1.0.pdf (https://www.sifive.com/documentation/chips/freedom-u540-c000-manual)

There are no configuration options set for this peripheral instance.



Peripheral [riscv.ovpworld.org/peripheral/PLIC/1.0] instance: plic

Licensing

Open Source Apache 2.0

Description

PLIC Interrupt Controller

Limitations

Sufficient functionality to boot Virtio BusyBear Linux Kernel. The num_priorities parameter is currently ignored. All 32 bits of priority registers are supported.

Reference

The RISC-V Instruction Set Manual Volume II: Privileged Architecture Version 1.10 (https://riscv.org/specifications/privileged-isa)
SiFive Freedom U540-C000 Manual FU540-C000-v1.0.pdf (https://www.sifive.com/documentation/chips/freedom-u540-c000-manual)

Table 7: Configuration options (attributes) set for instance 'plic'

AttributesValue
num_targets1
num_sources127



SiFivePlatforms
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