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SifivePRCI



OVP Peripheral Model: SifivePRCI



Model Specific Information

This page provides introductory usage information for an Imperas OVP peripheral behavioral model. The page is split into sections providing specific information for this peripheral, including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.

Description

Power Reset Clocking Interrupt (PRCI) block for SiFive FU540 chip

Limitations

Register only model. Reset values based on typical post-ZSBL configuration (1GHz coreclk, 500MHz tlclk).

Licensing

Open Source Apache 2.0

Reference

SiFive Freedom U540-C000 Manual FU540-C000-v1.0.pdf (https://www.sifive.com/documentation/chips/freedom-u540-c000-manual)

Location

The PRCI peripheral model is located in an Imperas/OVP installation at the VLNV: sifive.ovpworld.org / peripheral / PRCI / 1.0.



Net Ports

This model has the following net ports:

Table : Net Ports

NameTypeMust Be ConnectedDescription
resetinputF (False)



Bus Slave Ports

This model has the following bus slave ports:

Bus Slave Port: bport1

Table 1: Bus Slave Port: bport1

NameSize (bytes)Must Be ConnectedDescription
bport10x1000T (True)

Table 2: Bus Slave Port: bport1 Registers:

NameOffsetWidth (bits)DescriptionR/Wis Volatile
REG_hfxosccfg0x032
REG_corepllcfg00x432
REG_ddrpllcfg00xc32
REG_ddrpllcfg10x1032
REG_gemgxlpllcfg00x1c32
REG_gemgxlpllcfg10x2032
REG_coreclksel0x2432
REG_devicesresetreg0x2832



Platforms that use this peripheral component

Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.

Table 3: Publicly available platforms using peripheral 'PRCI'

Platform NameVendor
FU540sifive.ovpworld.org



SiFivePeripherals
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