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SifiveSpi



OVP Peripheral Model: SifiveSpi



Model Specific Information

This page provides introductory usage information for an Imperas OVP peripheral behavioral model. The page is split into sections providing specific information for this peripheral, including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.

Description

SiFive coreip-s51-arty SPI Registers (spi)

Licensing

Open Source Apache 2.0

Limitations

This model implements only the registers and contains no behaviour.

Reference

SiFive Freedom E SDK coreip-s51-arty Board Support Package details.

Location

The spi peripheral model is located in an Imperas/OVP installation at the VLNV: sifive.ovpworld.org / peripheral / spi / 1.0.



Net Ports

This model has the following net ports:

Table : Net Ports

NameTypeMust Be ConnectedDescription
resetNetinputF (False)



Bus Slave Ports

This model has the following bus slave ports:

Bus Slave Port: bport1

Table 1: Bus Slave Port: bport1

NameSize (bytes)Must Be ConnectedDescription
bport10x1000T (True)

Table 2: Bus Slave Port: bport1 Registers:

NameOffsetWidth (bits)DescriptionR/Wis Volatile
REG_sckdiv0x032Description Serial clock divisor Divisor for serial clock
REG_sckmode0x432Description Serial clock mode Serial clock phase Serial clock polarity
REG_csid0x1032Chip select ID
REG_csdef0x1432Chip select default
REG_csmode0x1832Description Chip select mode
REG_delay00x2832Description Delay control 0 CS to SCK Delay SCK to CS Delay
REG_delay10x2c32Description Delay control 1 Minimum CS inactive time Maximum interframe delay
REG_fmt0x4032Description Frame format SPI Protocol SPI endinanness SPI I/O Direction Number of bits per frame
REG_txdata0x4832Description Tx FIFO data Transmit data FIFO full flag
REG_rxdata0x4c32Description Rx FIFO data Received data FIFO empty flag
REG_txmark0x5032Description Tx FIFO watermark Transmit watermark
REG_rxmark0x5432Description Rx FIFO watermark receive watermark
REG_fctrl0x6032Description SPI flash interface control SPI Flash Mode Select
REG_ffmt0x6432Description SPI flash instruction format Enable sending of command Number of address bytes(0 to 4) Number of dummy cycles Protocol for transmitting command Protocol for transmitting address and padding Protocol for receiving data bytes Value of command byte First 8 bits to transmit during dummy cycles
REG_ie0x7032Description SPI interrupt enable Transmit watermark enable Receive watermark enable
REG_ip0x7432Description SPI interrupt pending Transmit watermark pending Receive watermark pending



Platforms that use this peripheral component

Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.

Table 3: Publicly available platforms using peripheral 'spi'

Platform NameVendor
coreip-s51-artysifive.ovpworld.org



SiFivePeripherals
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