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SifiveTeststatus



OVP Peripheral Model: SifiveTeststatus



Model Specific Information

This page provides introductory usage information for an Imperas OVP peripheral behavioral model. The page is split into sections providing specific information for this peripheral, including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.

Description

SiFive coreip-s51-arty Test Status Memory region.

Provides the test status region on the platform defintion that is used to terminate the execution of a test.

Licensing

Open Source Apache 2.0

Limitations

None.

Reference

SiFive Freedom E SDK coreip-s51-arty Board Support Package details.

Location

The teststatus peripheral model is located in an Imperas/OVP installation at the VLNV: sifive.ovpworld.org / peripheral / teststatus / 1.0.



Bus Slave Ports

This model has the following bus slave ports:

Bus Slave Port: bport1

Table : Bus Slave Port: bport1

NameSize (bytes)Must Be ConnectedDescription
bport10x1000T (True)


No address blocks have been defined for this slave port.



Platforms that use this peripheral component

Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.

Table 1: Publicly available platforms using peripheral 'teststatus'

Platform NameVendor
coreip-s51-artysifive.ovpworld.org



SiFivePeripherals
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