VinRZ5110 Processor Model was developed based on Imperas’ morphing technology and runs under the OVPSim Windows platform.
VinRZ5110 Processor Key Features
Key features of
VinRZ5110 Processor are:
1. 32-bit, 5-stage pipeline, Harvard Architecture RISC CPU
2. Five operating modes with optimized shadow register bank structure
- Supports very fast context switching for high priority interrupt modes
3. Single cycle 32X16 MAC enabling convergence of RISC and DSP
4. Native bus interface support for on-chip peripherals
- Realizes low interrupt latencies
5. Memory copy, atomic memory access, semaphore instructions
- Improves code density by a large margin
6. Low Power Modes support
- Power-down mode (triggered by en_idle instruction)
- Supports low power modes that facilitate CE designs
Downloads
 | DOWNLOAD VinRZ5110 model with example platform and application
OVP_Release_1.01.zip / 33.5 MB |
OVP_Release_1.01 Details
OVP_Release_1.01 consists of the complete toolchain binaries for
VinRZ5110 ISA and the
VinRZ5110
Processor model executable.
Toolchain was build under cygwin ported 32-bit Windows platform. Extract the vinrz_tool_chain tarball and
move the binaries to the "/usr/local" directory.
VinRZ5110_Model was build in the OVPSim simulator environment. The User Guide explains briefly about
"HOW TO USE" the
VinRZ5110 Processor Model in the OVPSim windows platform with example.
CategoryProcessor VinChipSystems
