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VinRZ5110 Processor Model


VinRZ5110 Processor Model was developed based on Imperas? morphing technology and runs under the OVPSim Windows platform.

VinRZ5110 Processor Key Features

Key features of VinRZ5110 Processor are:

1. 32-bit, 5-stage pipeline, Harvard Architecture RISC CPU

2. Five operating modes with optimized shadow register bank structure
  • Supports very fast context switching for high priority interrupt modes

3. Single cycle 32X16 MAC enabling convergence of RISC and DSP
  • Enables DSP applications

4. Native bus interface support for on-chip peripherals
  • Realizes low interrupt latencies

5. Memory copy, atomic memory access, semaphore instructions
  • Improves code density by a large margin

6. Low Power Modes support
  • Power-down mode (triggered by en_idle instruction)
  • Supports low power modes that facilitate CE designs


Downloads

Click to log in before viewing / downloadingDOWNLOAD VinRZ5110 model with example platform and application
OVP_Release_1.01.zip / 33.5 MB


OVP_Release_1.01 Details


OVP_Release_1.01 consists of the complete toolchain binaries for VinRZ5110 ISA and the VinRZ5110
Processor model executable.

Toolchain was build under cygwin ported 32-bit Windows platform. Extract the vinrz_tool_chain tarball and
move the binaries to the "/usr/local" directory.

VinRZ5110_Model was build in the OVPSim simulator environment. The User Guide explains briefly about
"HOW TO USE" the VinRZ5110 Processor Model in the OVPSim windows platform with example.


NOTE: Available in the files section is the zip file VinRZ5110.zip that contains the VinRZ5110 model source code updated to the current OVP release by OVP. All other downloads are maintained by VinChip Systems.



  Attachment Size Date Added
      OVP_Release_1.01.zip   33.5 MB   11/22/2016 5:52 pm
      VinRZ5110.igen.xml   4.12 KB   7/19/2018 4:30 pm
      VinRZ5110.zip   163.76 KB   7/19/2018 8:24 pm
 

Component Description for VinRZ5110/VinRZ5110.igen.xml

PROCESSOR

VinRZ5110

ELFCODE0
ENDIANeither
FAMILYVinchip
IMAGEFILEmodel
LIBRARYprocessor
PROCDOC$IMPERAS_HOME/ImperasLib/source/vinchip.com/processor/VinRZ5110/1.0/doc/OVP_Model_Specific_Information_VinRZ5110_generic.pdf
RELEASESTATUS2
USEINDEFAULTPLATFORMT
VENDORvinchip.com
VERSION1.0
VISIBILITY0

BUSMASTERPORT

INSTRUCTION

ADDRESSWIDTH32
ADDRESSWIDTHMAX32
ADDRESSWIDTHMIN32
MUSTBECONNECTEDT
DOCSECTION
doc
TEXTDescription
DOCTEXT
txt
TEXTUsed to fetch code for execution

BUSMASTERPORT

DATA

ADDRESSWIDTH32
ADDRESSWIDTHMAX32
ADDRESSWIDTHMIN32
MUSTBECONNECTEDF
DOCSECTION
doc
TEXTDescription
DOCTEXT
txt
TEXTUsed to read & write data

COMMAND

isync

DOCSECTION
doc
TEXTDescription
DOCTEXT
txt
TEXTspecify instruction address range for synchronous execution
COMMANDARG
addresshi
TYPEUns64
DOCSECTION
doc
TEXTDescription
DOCTEXTtxt
TEXTend address of synchronous execution range
COMMANDARG
addresslo
TYPEUns64
DOCSECTION
doc
TEXTDescription
DOCTEXTtxt
TEXTstart address of synchronous execution range

COMMAND

itrace

DOCSECTION
doc
TEXTDescription
DOCTEXT
txt
TEXTenable or disable instruction tracing
COMMANDARG
after
TYPEUns64
DOCSECTION
doc
TEXTDescription
DOCTEXTtxt
TEXTapply after this many instructions
COMMANDARG
enable
TYPEBoolean
DOCSECTION
doc
TEXTDescription
DOCTEXTtxt
TEXTenable instruction tracing
COMMANDARG
instructioncount
TYPEBoolean
DOCSECTION
doc
TEXTDescription
DOCTEXTtxt
TEXTinclude the instruction number in each trace
COMMANDARG
off
TYPEBoolean
DOCSECTION
doc
TEXTDescription
DOCTEXTtxt
TEXTdisable instruction tracing
COMMANDARG
on
TYPEBoolean
DOCSECTION
doc
TEXTDescription
DOCTEXTtxt
TEXTenable instruction tracing
COMMANDARG
registerchange
TYPEBoolean
DOCSECTION
doc
TEXTDescription
DOCTEXTtxt
TEXTshow registers changed by this instruction
COMMANDARG
registers
TYPEBoolean
DOCSECTION
doc
TEXTDescription
DOCTEXTtxt
TEXTshow registers after each trace

FILEVERSION

_version_0

MAJOR1
MINOR0


CategoryProcessor VinChipSystems
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