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VirtIO



OVP Virtual Platform: virtio

This page provides detailed information about the OVP Virtual Platform Model of the riscv.ovpworld.org virtio platform.

Licensing

Open Source Apache 2.0

Description

Virtio System Platform to boot BusyBear-Linux Kernel

Reference

Virtio System Platform

Limitations

Sufficient functionality to boot BusyBear-Linux Kernel using the Virtio platform

Location

The virtio virtual platform is located in an Imperas/OVP installation at the VLNV: riscv.ovpworld.org / module / virtio / 1.0.

Platform Summary

Table : Components in platform

TypeInstanceVendorComponent
Processorhart0riscv.ovpworld.orgriscvRVB64I
PeripheralVBD0ovpworld.orgVirtioBlkMMIO
PeripheralVND0ovpworld.orgVirtioNetMMIO
PeripheralethBridgeovpworld.orgvEthernet_Bridge
Peripheralvirtio_mmio3ovpworld.orgtrap
Peripheralvirtio_mmio4ovpworld.orgtrap
Peripheralvirtio_mmio5ovpworld.orgtrap
Peripheralvirtio_mmio6ovpworld.orgtrap
Peripheralvirtio_mmio7ovpworld.orgtrap
Peripheralvirtio_mmio8ovpworld.orgtrap
Peripheralclintriscv.ovpworld.orgCLINT
Peripheralplicriscv.ovpworld.orgPLIC
PeripheraluartTTY0national.ovpworld.org16550
PeripheralsmartLoaderriscv.ovpworld.orgSmartLoaderRV64Linux
Memorybootramovpworld.orgram
Memorymainovpworld.orgram
Busbus0(builtin)address width:48

Platform Simulation Attributes

Table 1: Platform Simulation Attributes

AttributeValueDescription
stoponctrlcstoponctrlcStop on control-C



Processor [riscv.ovpworld.org/processor/riscv/1.0] instance: hart0

Processor model type: 'riscv' variant 'RVB64I' definition

Imperas OVP processor models support multiple variants and details of the variants implemented in this model can be found in:
- the Imperas installation located at ImperasLib/source/riscv.ovpworld.org/processor/riscv/1.0/doc
- the OVP website: OVP_Model_Specific_Information_riscv_RVB64I.pdf

Description

RISC-V RVB64I 64-bit processor model

Licensing

This Model is released under the Open Source Apache 2.0

Extensions

The model has the following architectural extensions enabled, and the following bits in the misa CSR Extensions field will be set upon reset:
misa bit 8: RV32I/64I/128I base ISA
To specify features that can be dynamically enabled or disabled by writes to the misa register in addition to those listed above, use parameter "add_Extensions_mask". This is a string parameter containing the feature letters to add; for example, value "DV" indicates that double-precision floating point and the Vector Extension can be enabled or disabled by writes to the misa register.
Legacy parameter "misa_Extensions_mask" can also be used. This Uns32-valued parameter specifies all writable bits in the misa Extensions field, replacing any value defined in the base variant.
Note that any features that are indicated as present in the misa mask but absent in the misa will be ignored. See the next section.
Legacy parameter "misa_Extensions" can also be used. This Uns32-valued parameter specifies the reset value for the misa CSR Extensions field, replacing any value defined in the base variant.

Available (But Not Enabled) Extensions

The following extensions are supported by the model, but not enabled by default in this variant:
misa bit 0: extension A (atomic instructions) (NOT ENABLED)
misa bit 2: extension C (compressed instructions) (NOT ENABLED)
misa bit 3: extension D (double-precision floating point) (NOT ENABLED)
misa bit 4: RV32E base ISA (NOT ENABLED)
misa bit 5: extension F (single-precision floating point) (NOT ENABLED)
misa bit 12: extension M (integer multiply/divide instructions) (NOT ENABLED)
misa bit 13: extension N (user-level interrupts) (NOT ENABLED)
misa bit 18: extension S (Supervisor mode) (NOT ENABLED)
misa bit 20: extension U (User mode) (NOT ENABLED)
misa bit 21: extension V (vector instructions) (NOT ENABLED)
misa bit 23: extension X (non-standard extensions present) (NOT ENABLED)
To add features from this list to the base variant, use parameter "add_Extensions". This is a string parameter containing the feature letters to add; for example, value "DV" indicates that double-precision floating point and the Vector Extension should be enabled, if they are absent.

General Features

On this variant, the Machine trap-vector base-address register (mtvec) is writable. It can instead be configured as read-only using parameter "mtvec_is_ro".
Values written to "mtvec" are masked using the value 0xfffffffffffffffd. A different mask of writable bits may be specified using parameter "mtvec_mask" if required. In addition, when Vectored interrupt mode is enabled, parameter "tvec_align" may be used to specify additional hardware-enforced base address alignment. In this variant, "tvec_align" defaults to 0, implying no alignment constraint.
The initial value of "mtvec" is 0x0. A different value may be specified using parameter "mtvec" if required.
On reset, the model will restart at address 0x0. A different reset address may be specified using parameter "reset_address" if required.
On an NMI, the model will restart at address 0x0. A different NMI address may be specified using parameter "nmi_address" if required.
WFI will halt the processor until an interrupt occurs. It can instead be configured as a NOP using parameter "wfi_is_nop". WFI timeout wait is implemented with a time limit of 0 (i.e. WFI causes an Illegal Instruction trap in Supervisor mode when mstatus.TW=1).
The "cycle" CSR is implemented in this variant. Set parameter "cycle_undefined" to True to instead specify that "cycle" is unimplemented and reads of it should trap to Machine mode.
The "time" CSR is implemented in this variant. Set parameter "time_undefined" to True to instead specify that "time" is unimplemented and reads of it should trap to Machine mode. Usually, the value of the "time" CSR should be provided by the platform - see notes below about the artifact "CSR" bus for information about how this is done.
The "instret" CSR is implemented in this variant. Set parameter "instret_undefined" to True to instead specify that "instret" is unimplemented and reads of it should trap to Machine mode.
Unaligned memory accesses are not supported by this variant. Set parameter "unaligned" to "T" to enable such accesses.
A PMP unit is not implemented by this variant. Set parameter "PMP_registers" to indicate that the unit should be implemented with that number of PMP entries.

Interrupts

The "reset" port is an active-high reset input. The processor is halted when "reset" goes high and resumes execution from the reset address specified using the "reset_address" parameter when the signal goes low. The "mcause" register is cleared to zero.
The "nmi" port is an active-high NMI input. The processor is halted when "nmi" goes high and resumes execution from the address specified using the "nmi_address" parameter when the signal goes low. The "mcause" register is cleared to zero.
All other interrupt ports are active high.

Debug Mask

It is possible to enable model debug messages in various categories. This can be done statically using the "override_debugMask" parameter, or dynamically using the "debugflags" command. Enabled messages are specified using a bitmask value, as follows:
Value 0x002: enable debugging of PMP and virtual memory state;
Value 0x004: enable debugging of interrupt state.
All other bits in the debug bitmask are reserved and must not be set to non-zero values.

Integration Support

This model implements a number of non-architectural pseudo-registers and other features to facilitate integration.

CSR Register External Implementation

If parameter "enable_CSR_bus" is True, an artifact 16-bit bus "CSR" is enabled. Slave callbacks installed on this bus can be used to implement modified CSR behavior (use opBusSlaveNew or icmMapExternalMemory, depending on the client API). A CSR with index 0xABC is mapped on the bus at address 0xABC0; as a concrete example, implementing CSR "time" (number 0xC01) externally requires installation of callbacks at address 0xC010 on the CSR bus.

Limitations

Instruction pipelines are not modeled in any way. All instructions are assumed to complete immediately. This means that instruction barrier instructions (e.g. fence.i) are treated as NOPs, with the exception of any Illegal Instruction behavior, which is modeled.
Caches and write buffers are not modeled in any way. All loads, fetches and stores complete immediately and in order, and are fully synchronous. Data barrier instructions (e.g. fence) are treated as NOPs, with the exception of any Illegal Instruction behavior, which is modeled.
Real-world timing effects are not modeled: all instructions are assumed to complete in a single cycle.
Hardware Performance Monitor and Debug registers are not implemented and hardwired to zero.

Verification

All instructions have been extensively tested by Imperas, using tests generated specifically for this model and also reference tests from https://github.com/riscv/riscv-tests.
Also reference tests have been used from various sources including:
https://github.com/riscv/riscv-tests
https://github.com/ucb-bar/riscv-torture
The Imperas OVPsim RISC-V models are used in the RISC-V FoundationsCompliance Framework as a functional Golden Reference:
https://github.com/riscv/riscv-compliance
where the simulated model is used to provide the reference signaturesfor compliance testing.The Imperas OVPsim RISC-V models are used as reference in both opensource and commercial instruction stream test generators for hardwaredesign verification, for example:
http://valtrix.in/sting/ from Valtrix
https://github.com/google/riscv-dv from Google
The Imperas OVPsim RISC-V models are also used by commercial and opensource RISC-V Core RTL developers as a reference to ensure correctfunctionality of their IP.

References

The Model details are based upon the following specifications:
RISC-V Instruction Set Manual, Volume I: User-Level ISA (User Architecture Version 20190305-Base-Ratification)
RISC-V Instruction Set Manual, Volume II: Privileged Architecture (Privileged Architecture Version 20190405-Priv-MSU-Ratification)

Instance Parameters

Several parameters can be specified when a processor is instanced in a platform. For this processor instance 'hart0' it has been instanced with the following parameters:

Table 2: Processor Instance 'hart0' Parameters (Configurations)

ParameterValueDescription
simulateexceptionssimulateexceptionsCauses the processor simulate exceptions instead of halting
mips50The nominal MIPS for the processor

Table 3: Processor Instance 'hart0' Parameters (Attributes)

Parameter NameValueType
variantRVB64Ienum
add_ExtensionsMAFDCSUstring
reset_address0x1000Uns64
time_undefinedTruebool

Memory Map for processor 'hart0' bus: 'bus0'

Processor instance 'hart0' is connected to bus 'bus0' using master port 'INSTRUCTION'.

Processor instance 'hart0' is connected to bus 'bus0' using master port 'DATA'.

Table 4: Memory Map ( 'hart0' / 'bus0' [width: 48] )

Lo AddressHi AddressInstanceComponent
remappableremappablevirtio_mmio3trap
remappableremappablevirtio_mmio4trap
remappableremappablevirtio_mmio5trap
remappableremappablevirtio_mmio6trap
remappableremappablevirtio_mmio7trap
remappableremappablevirtio_mmio8trap
0x10000x2FFFbootramram
0x20000000x200BFFFclintCLINT
0xC0000000xFFFFFFFplicPLIC
0x100000000x10000007uartTTY016550
0x100010000x100011FFVBD0VirtioBlkMMIO
0x100020000x100021FFVND0VirtioNetMMIO
0x800000000x87FFFFFFmainram

Net Connections to processor: 'hart0'

Table 5: Processor Net Connections ( 'hart0' )

Net PortNetInstanceComponent
MExternalInterruptirqT0plicPLIC
SExternalInterruptirqT1plicPLIC
MTimerInterruptMTimerInterrupt0clintCLINT
MSWInterruptMSWInterrupt0clintCLINT



Peripheral Instances



Peripheral [ovpworld.org/peripheral/VirtioBlkMMIO/1.0] instance: VBD0

Description

VIRTIO version 1 mmio block device This model implements a VIRTIO MMIO block device as described in: http://docs.oasis-open.org/virtio/virtio/v1.0/virtio-v1.0.pdf. Use the VB_DRIVE parameter to specify the disk image file to use. Set the VB_DRIVE_DELTA parameter to 1 to prevent writes to disk during simulation from changing the image file.

Limitations

Only supports the Legacy (Device Version 1) interface. Only little endian guests are supported.

Licensing

Open Source Apache 2.0

Reference

http://docs.oasis-open.org/virtio/virtio/v1.0/virtio-v1.0.pdf

There are no configuration options set for this peripheral instance.



Peripheral [ovpworld.org/peripheral/VirtioNetMMIO/1.0] instance: VND0

Description

VIRTIO version 1 mmio block device This model implements a VIRTIO MMIO net device as described in: http://docs.oasis-open.org/virtio/virtio/v1.0/virtio-v1.0.pdf.

Limitations

Only supports the Legacy (Device Version 1) interface. Only little endian guests are supported.

Licensing

Open Source Apache 2.0

Reference

http://docs.oasis-open.org/virtio/virtio/v1.0/virtio-v1.0.pdf

There are no configuration options set for this peripheral instance.



Peripheral [ovpworld.org/peripheral/vEthernet_Bridge/1.0] instance: ethBridge

Description

Bridges between a packetnet and the host's network

Limitations

None.

There are no configuration options set for this peripheral instance.



Peripheral [ovpworld.org/peripheral/trap/1.0] instance: virtio_mmio3

Description

Open a port and allocate a region that is defined by parameters.
The region can be configured to act as standard memory or can report read/write accesses.

Licensing

Open Source Apache 2.0

Limitations

This peripheral cannot be used in a hardware description used to generate a TLM platform.

Reference

This is not based upon the operation of a real device but is intended to be used for bring up and development of new virtual platforms.

Table 6: Configuration options (attributes) set for instance 'virtio_mmio3'

AttributesValue
portAddress0x10003000
portSize4096
cbEnableTrue



Peripheral [ovpworld.org/peripheral/trap/1.0] instance: virtio_mmio4

Description

Open a port and allocate a region that is defined by parameters.
The region can be configured to act as standard memory or can report read/write accesses.

Licensing

Open Source Apache 2.0

Limitations

This peripheral cannot be used in a hardware description used to generate a TLM platform.

Reference

This is not based upon the operation of a real device but is intended to be used for bring up and development of new virtual platforms.

Table 7: Configuration options (attributes) set for instance 'virtio_mmio4'

AttributesValue
portAddress0x10004000
portSize4096
cbEnableTrue



Peripheral [ovpworld.org/peripheral/trap/1.0] instance: virtio_mmio5

Description

Open a port and allocate a region that is defined by parameters.
The region can be configured to act as standard memory or can report read/write accesses.

Licensing

Open Source Apache 2.0

Limitations

This peripheral cannot be used in a hardware description used to generate a TLM platform.

Reference

This is not based upon the operation of a real device but is intended to be used for bring up and development of new virtual platforms.

Table 8: Configuration options (attributes) set for instance 'virtio_mmio5'

AttributesValue
portAddress0x10005000
portSize4096
cbEnableTrue



Peripheral [ovpworld.org/peripheral/trap/1.0] instance: virtio_mmio6

Description

Open a port and allocate a region that is defined by parameters.
The region can be configured to act as standard memory or can report read/write accesses.

Licensing

Open Source Apache 2.0

Limitations

This peripheral cannot be used in a hardware description used to generate a TLM platform.

Reference

This is not based upon the operation of a real device but is intended to be used for bring up and development of new virtual platforms.

Table 9: Configuration options (attributes) set for instance 'virtio_mmio6'

AttributesValue
portAddress0x10006000
portSize4096
cbEnableTrue



Peripheral [ovpworld.org/peripheral/trap/1.0] instance: virtio_mmio7

Description

Open a port and allocate a region that is defined by parameters.
The region can be configured to act as standard memory or can report read/write accesses.

Licensing

Open Source Apache 2.0

Limitations

This peripheral cannot be used in a hardware description used to generate a TLM platform.

Reference

This is not based upon the operation of a real device but is intended to be used for bring up and development of new virtual platforms.

Table 10: Configuration options (attributes) set for instance 'virtio_mmio7'

AttributesValue
portAddress0x10007000
portSize4096
cbEnableTrue



Peripheral [ovpworld.org/peripheral/trap/1.0] instance: virtio_mmio8

Description

Open a port and allocate a region that is defined by parameters.
The region can be configured to act as standard memory or can report read/write accesses.

Licensing

Open Source Apache 2.0

Limitations

This peripheral cannot be used in a hardware description used to generate a TLM platform.

Reference

This is not based upon the operation of a real device but is intended to be used for bring up and development of new virtual platforms.

Table 11: Configuration options (attributes) set for instance 'virtio_mmio8'

AttributesValue
portAddress0x10008000
portSize4096
cbEnableTrue



Peripheral [riscv.ovpworld.org/peripheral/CLINT/1.0] instance: clint

Licensing

Open Source Apache 2.0

Description

Risc-V Core Local Interruptor (CLINT). Use the num_harts parameter to specify the number of harts suported (default 1). For each supported hart there will be an MTimerInterruptN and MSWInterruptN net port, plus msipN and mtimecmpN registers implemented, where N is a value from 0..num_harts-1 There is also a single mtime register.

Limitations

Writes to mtime register are not supported

Reference

SiFive Freedom U540-C000 Manual FU540-C000-v1.0.pdf (https://www.sifive.com/documentation/chips/freedom-u540-c000-manual)

Table 12: Configuration options (attributes) set for instance 'clint'

AttributesValue
num_harts1
clockMHz25.0



Peripheral [riscv.ovpworld.org/peripheral/PLIC/1.0] instance: plic

Licensing

Open Source Apache 2.0

Description

PLIC Interrupt Controller

Limitations

Sufficient functionality to boot Virtio BusyBear Linux Kernel. The num_priorities parameter is currently ignored. All 32 bits of priority registers are supported.

Reference

The RISC-V Instruction Set Manual Volume II: Privileged Architecture Version 1.10 (https://riscv.org/specifications/privileged-isa)
SiFive Freedom U540-C000 Manual FU540-C000-v1.0.pdf (https://www.sifive.com/documentation/chips/freedom-u540-c000-manual)

Table 13: Configuration options (attributes) set for instance 'plic'

AttributesValue
num_sources10
num_targets2



Peripheral [national.ovpworld.org/peripheral/16550/1.0] instance: uartTTY0

Licensing

Open Source Apache 2.0

Description

16550 UART model
The serial input/output from the simulator is implemented using the Serial Device Support described in OVP BHM and PPM API Functions Reference, which describes the parameters that control how the model interacts with the host computer.
Interrupts and FIFOs are supported.
Registers are aligned on 1 byte boundaries.

Limitations

Resolution of the baud rate is limited to the simulation time slice (aka quantum) size.
Values written to the MCR are ignored. Loopback mode is not supported.
The LSR is read-only. The model never sets the LSR 'Parity Error', 'Framing Error', 'Break Interrupt' or 'Error in RCVR FIFO' bits.
The MSR 'Data Set Ready' and 'Clear To Send' bits are set at reset and all other MSR bits are cleared. MSR bits will only be changed by writes to the MSR and values written to the Modem Status Register do not effect the operation of the model.

Reference

PC16550D Universal Asynchronous Receiver/Transmitter with FIFOs datasheet (http://www.ti.com/lit/ds/symlink/pc16550d.pdf)

There are no configuration options set for this peripheral instance.



Peripheral [riscv.ovpworld.org/peripheral/SmartLoaderRV64Linux/1.0] instance: smartLoader

Licensing

Open Source Apache 2.0

Description

Psuedo-peripheral to insert boot code for a Riscv 64-bit Linux kernel boot. Loads simulated memory with a device tree blob file and boot code to set regs and jump to a Risc-v Linux Kernel.

Limitations

Only supports little endian

Reference

RISC-V Linux Kernel development

Table 14: Configuration options (attributes) set for instance 'smartLoader'

AttributesValue
bootaddr0x80000000
slbootaddr0x1000



RiscVplatforms
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