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XilinxAxiIntc



OVP Peripheral Model: XilinxAxiIntc



Model Specific Information

This page provides introductory usage information for an Imperas OVP peripheral behavioral model. The page is split into sections providing specific information for this peripheral, including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.

Description

Microblaze LogiCORE IP AXI Interrupt Controller

Licensing

Open Source Apache 2.0

Limitations

Implements the basic interrupt processing behavior

Does not implement interrupt cascade

Reference

PG099 October 4, 2017 v4.1

Location

The axi-intc peripheral model is located in an Imperas/OVP installation at the VLNV: xilinx.ovpworld.org / peripheral / axi-intc / 1.0.



Peripheral Instance Parameters

This model accepts the following parameters:

Table : Peripheral Parameters

NameTypeDescription
C_HAS_IPRboolThe Interrupt Pending Register exists
C_HAS_SIEboolThe Set Interrupt Enables Register exists
C_HAS_CIEboolThe Clear Interrupt Enables Register exists
C_HAS_IMRboolThe Interrupt Mode Register exists
C_HAS_FASTboolThe Fast Interrupt Logic is enabled
C_EN_CASCADE_MODEboolSet to enable the cascading of interrupts
C_CASCADE_MASTERboolSet when the cascade master
C_NUM_INTR_INPUTSuns32Set the number of active hardware interrupt inputs (default 16)
C_NUM_SW_INTRuns32Set the number of software interrupts (default 4)



Net Ports

This model has the following net ports:

Table 1: Net Ports

NameTypeMust Be ConnectedDescription
intr0inputF (False)
intr1inputF (False)
intr2inputF (False)
intr3inputF (False)
intr4inputF (False)
intr5inputF (False)
intr6inputF (False)
intr7inputF (False)
intr8inputF (False)
intr9inputF (False)
intr10inputF (False)
intr11inputF (False)
intr12inputF (False)
intr13inputF (False)
intr14inputF (False)
intr15inputF (False)
intr16inputF (False)
intr17inputF (False)
intr18inputF (False)
intr19inputF (False)
intr20inputF (False)
intr21inputF (False)
intr22inputF (False)
intr23inputF (False)
intr24inputF (False)
intr25inputF (False)
intr26inputF (False)
intr27inputF (False)
intr28inputF (False)
intr29inputF (False)
intr30inputF (False)
intr31inputF (False)
irq_ininputF (False)
irq_addr_ininputF (False)
irq_ack_outoutputF (False)
irqoutputF (False)
irq_ackinputF (False)
irq_addr_outoutputF (False)



Bus Slave Ports

This model has the following bus slave ports:

Bus Slave Port: bport1

Table 2: Bus Slave Port: bport1

NameSize (bytes)Must Be ConnectedDescription
bport10x200T (True)

Table 3: Bus Slave Port: bport1 Registers:

NameOffsetWidth (bits)DescriptionR/Wis Volatile
ab_ISR0x032Interrupt Status Register (ISR)
ab_IPR0x432Interrupt Pending Register (IPR)
ab_IER0x832Interrupt Enable Register (IER)
ab_IAR0xc32Interrupt Acknowledge Register (IAR)
ab_SIE0x1032Set Interrupt Enables (SIE)
ab_CIE0x1432Clear Interrupt Enables (CIE)
ab_IVR0x1832Interrupt Vector Register (IVR)
ab_MER0x1c32Description Master Enable Register (MER)
ab_IMR0x2032Interrupt Mode Register (IMR)
ab_ILR0x2432Interrupt Level Register (ILR)
ab_IVAR00x10032IVAR Interrupt Vector Address Register (IVAR)
ab_IVAR10x10432IVAR Interrupt Vector Address Register (IVAR)
ab_IVAR20x10832IVAR Interrupt Vector Address Register (IVAR)
ab_IVAR30x10c32IVAR Interrupt Vector Address Register (IVAR)
ab_IVAR40x11032IVAR Interrupt Vector Address Register (IVAR)
ab_IVAR50x11432IVAR Interrupt Vector Address Register (IVAR)
ab_IVAR60x11832IVAR Interrupt Vector Address Register (IVAR)
ab_IVAR70x11c32IVAR Interrupt Vector Address Register (IVAR)
ab_IVAR80x12032IVAR Interrupt Vector Address Register (IVAR)
ab_IVAR90x12432IVAR Interrupt Vector Address Register (IVAR)
ab_IVAR100x12832IVAR Interrupt Vector Address Register (IVAR)
ab_IVAR110x12c32IVAR Interrupt Vector Address Register (IVAR)
ab_IVAR120x13032IVAR Interrupt Vector Address Register (IVAR)
ab_IVAR130x13432IVAR Interrupt Vector Address Register (IVAR)
ab_IVAR140x13832IVAR Interrupt Vector Address Register (IVAR)
ab_IVAR150x13c32IVAR Interrupt Vector Address Register (IVAR)
ab_IVAR160x14032IVAR Interrupt Vector Address Register (IVAR)
ab_IVAR170x14432IVAR Interrupt Vector Address Register (IVAR)
ab_IVAR180x14832IVAR Interrupt Vector Address Register (IVAR)
ab_IVAR190x14c32IVAR Interrupt Vector Address Register (IVAR)
ab_IVAR200x15032IVAR Interrupt Vector Address Register (IVAR)
ab_IVAR210x15432IVAR Interrupt Vector Address Register (IVAR)
ab_IVAR220x15832IVAR Interrupt Vector Address Register (IVAR)
ab_IVAR230x15c32IVAR Interrupt Vector Address Register (IVAR)
ab_IVAR240x16032IVAR Interrupt Vector Address Register (IVAR)
ab_IVAR250x16432IVAR Interrupt Vector Address Register (IVAR)
ab_IVAR260x16832IVAR Interrupt Vector Address Register (IVAR)
ab_IVAR270x16c32IVAR Interrupt Vector Address Register (IVAR)
ab_IVAR280x17032IVAR Interrupt Vector Address Register (IVAR)
ab_IVAR290x17432IVAR Interrupt Vector Address Register (IVAR)
ab_IVAR300x17832IVAR Interrupt Vector Address Register (IVAR)
ab_IVAR310x17c32IVAR Interrupt Vector Address Register (IVAR)



Platforms that use this peripheral component

Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.

Table 4: Publicly available platforms using peripheral 'axi-intc'

Platform NameVendor
Zynq_PL_TTELNoC_processing_node_public_demonstratorsafepower.ovpworld.org
Zynq_PL_TTELNoC_sensor_actor_node_public_demonstratorsafepower.ovpworld.org



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