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XilinxAxiPcie



OVP Peripheral Model: XilinxAxiPcie



Model Specific Information

This page provides introductory usage information for an Imperas OVP peripheral behavioral model. The page is split into sections providing specific information for this peripheral, including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.

Licensing

Open Source Apache 2.0

Description

Xilinx AXI to PCI Express bridge.

Diagnostic levels:

PCIE_SLAVE 0x03

PCIE_CONFIG_MASTER 0x04

PCIE_EMPTY 0x08

INT_ACK 0x10

MAIN_BUS 0x20

INFO 0x40

Limitations

This model has sufficient functionality to allow a Linux Kernel to Boot.

Reference

LogiCORE IP AXI Bridge for PCI Express v2.3 Product Guide April 2, 2014.

Location

The axi-pcie peripheral model is located in an Imperas/OVP installation at the VLNV: xilinx.ovpworld.org / peripheral / axi-pcie / 1.0.



Peripheral Instance Parameters

This model accepts the following parameters:

Table : Peripheral Parameters

NameTypeDescription
PCIbusuns32Specify which PCI Express bus the device occupies.
PCIslotuns32Specify which PCI Express slot the device occupies.
PCIfunctionuns32Specify which PCI Express function the device implements.



Net Ports

This model has the following net ports:

Table 1: Net Ports

NameTypeMust Be ConnectedDescription
intOutoutputF (False)
intAinputF (False)
intBinputF (False)
intCinputF (False)
intDinputF (False)



Bus Master Ports

This model has the following bus master ports:

Bus Master Port: PCIconfigM

Table 2: PCIconfigM

NameAddress Width (bits)Description
PCIconfigM28

Bus Master Port: PCIackM

Table 3: PCIackM

NameAddress Width (bits)Description
PCIackM0



Bus Slave Ports

This model has the following bus slave ports:

Bus Slave Port: ecam

Table 4: Bus Slave Port: ecam

NameSize (bytes)Must Be ConnectedDescription
ecam0x1000T (True)


No address blocks have been defined for this slave port.

Bus Slave Port: busPort

Table 5: Bus Slave Port: busPort

NameSize (bytes)Must Be ConnectedDescription
busPort0x1000T (True)


No address blocks have been defined for this slave port.

Bus Slave Port: PCIconfig

Table 6: Bus Slave Port: PCIconfig

NameSize (bytes)Must Be ConnectedDescription
PCIconfig0x1F (False)


No address blocks have been defined for this slave port.


XilinxPeripherals
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