OVP Peripheral Model: XilinxAxiPcie
Model Specific Information
This page provides introductory usage information for an Imperas OVP peripheral behavioral model.
The page is split into sections providing specific information for this peripheral,
including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.
Licensing
Open Source Apache 2.0
Description
Xilinx AXI to PCI Express bridge.
Diagnostic levels:
PCIE_SLAVE 0x03
PCIE_CONFIG_MASTER 0x04
PCIE_EMPTY 0x08
INT_ACK 0x10
MAIN_BUS 0x20
INFO 0x40
Limitations
This model has sufficient functionality to allow a Linux Kernel to Boot.
Reference
LogiCORE IP AXI Bridge for PCI Express v2.3 Product Guide April 2, 2014.
Location
The axi-pcie peripheral model is located in an Imperas/OVP installation at the VLNV: xilinx.ovpworld.org / peripheral / axi-pcie / 1.0.
Peripheral Instance Parameters
This model accepts the following parameters:
Table : Peripheral Parameters
Name | Type | Description |
---|
PCIbus | uns32 | Specify which PCI Express bus the device occupies. |
PCIslot | uns32 | Specify which PCI Express slot the device occupies. |
PCIfunction | uns32 | Specify which PCI Express function the device implements. |
Net Ports
This model has the following net ports:
Table 1: Net Ports
Name | Type | Must Be Connected | Description |
---|
intOut | output | F (False) | |
intA | input | F (False) | |
intB | input | F (False) | |
intC | input | F (False) | |
intD | input | F (False) | |
Bus Master Ports
This model has the following bus master ports:
Bus Master Port: PCIconfigM
Table 2: PCIconfigM
Name | Address Width (bits) | Description |
---|
PCIconfigM | 28 | |
Bus Master Port: PCIackM
Table 3: PCIackM
Name | Address Width (bits) | Description |
---|
PCIackM | 0 | |
Bus Slave Ports
This model has the following bus slave ports:
Bus Slave Port: ecam
Table 4: Bus Slave Port: ecam
Name | Size (bytes) | Must Be Connected | Description |
---|
ecam | 0x1000 | T (True) | |
No address blocks have been defined for this slave port.
Bus Slave Port: busPort
Table 5: Bus Slave Port: busPort
Name | Size (bytes) | Must Be Connected | Description |
---|
busPort | 0x1000 | T (True) | |
No address blocks have been defined for this slave port.
Bus Slave Port: PCIconfig
Table 6: Bus Slave Port: PCIconfig
Name | Size (bytes) | Must Be Connected | Description |
---|
PCIconfig | 0x1 | F (False) | |
No address blocks have been defined for this slave port.