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XilinxXpsMchEmc



OVP Peripheral Model: XilinxXpsMchEmc



Model Specific Information

This page provides introductory usage information for an Imperas OVP peripheral behavioral model. The page is split into sections providing specific information for this peripheral, including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.

Description

Microblaze LogiCORE IP XPS MCH EMC Multi Channel External Memory Controller

Licensing

Open Source Apache 2.0

Limitations

This model implements the registers but has no functional behavior

Reference

DS575 June 22, 2010 v3.01a

Location

The xps-mch-emc peripheral model is located in an Imperas/OVP installation at the VLNV: xilinx.ovpworld.org / peripheral / xps-mch-emc / 1.0.



Net Ports

This model has the following net ports:

Table : Net Ports

NameTypeMust Be ConnectedDescription
InterruptoutputF (False)



Bus Slave Ports

This model has the following bus slave ports:

Bus Slave Port: plb

Table 1: Bus Slave Port: plb

NameSize (bytes)Must Be ConnectedDescription
plb0x2000000T (True)


No address blocks have been defined for this slave port.



Platforms that use this peripheral component

Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.

Table 2: Publicly available platforms using peripheral 'xps-mch-emc'

Platform NameVendor
XilinxML505xilinx.ovpworld.org
XilinxML505xilinx.ovpworld.org



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