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XilinxXpsTimer



OVP Peripheral Model: XilinxXpsTimer



Model Specific Information

This page provides introductory usage information for an Imperas OVP peripheral behavioral model. The page is split into sections providing specific information for this peripheral, including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.

Description

Microblaze LogiCORE IP XPS Timer/Counter

Licensing

Open Source Apache 2.0

Limitations

Resolution of this timer is limited to the simulation time slice (aka quantum) size

Reference

DS573 April 19, 2010 v1.02a

Location

The xps-timer peripheral model is located in an Imperas/OVP installation at the VLNV: xilinx.ovpworld.org / peripheral / xps-timer / 1.0.



Peripheral Instance Parameters

This model accepts the following parameters:

Table : Peripheral Parameters

NameTypeDescription
frequencyuns32Specify frequency of the counters in Hz (default 125000000 Hz)
endianstringSpecify the endian of the processor interface (default big endian)



Net Ports

This model has the following net ports:

Table 1: Net Ports

NameTypeMust Be ConnectedDescription
InterruptoutputF (False)



Bus Slave Ports

This model has the following bus slave ports:

Bus Slave Port: plb

Table 2: Bus Slave Port: plb

NameSize (bytes)Must Be ConnectedDescription
plb0x20T (True)

Table 3: Bus Slave Port: plb Registers:

NameOffsetWidth (bits)DescriptionR/Wis Volatile
REG_TCSR00x032
REG_TLR00x432
REG_TCR00x832
REG_TCSR10x1032
REG_TLR10x1432
REG_TCR10x1832



Platforms that use this peripheral component

Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.

Table 4: Publicly available platforms using peripheral 'xps-timer'

Platform NameVendor
XilinxML505xilinx.ovpworld.org
XilinxML505xilinx.ovpworld.org



XilinxPeripherals
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